The digital speech interpolation (DSI) module is the most complex unit in a TDMA traffic terminal and the one which presents the most options to the equipment designer. The merits of various design approaches are contrasted and compared. The options arise in the choice of architectures and technologies for the realization of the module. There are several aspects to architectural choice in the unit design involving the amount of storage and nature of storage in the unit, the nature and type of the high speed interface, the nature of echo protection features, FEC encoding, and the degree and nature of the human interface for test and maintenance. In terms of storage, because the interpolation process takes time, the unit is by necessity memory-oriented and efficient choice of memory architecture is important. The two principal design choices here may be called "order and storage" and "storage and order." Store-and-order implies storage of data on all received channels (whether they are to be processed or not) followed by data routing for selected channels. Order-and-store implies immediate selection of that traffic to be processed. The architecture is also influenced by the choice of interface between the DSI and the "satellite" side equipment. The principal choice lies between word- and bit-oriented data transmission, but there are tradeoffs involving handshaking for control signals as well. The INTELSAT specifications governing DSI module performance give designers of specific equipment wide latitude in the human interface for testing and maintenance features and for the extent to which the unit will support the accumulation of traffic data statistics. The implications to system architecture of these choices are dealt with. Whatever the architecture may be, DSI module design requires a judicious selection of technologies. Among the questions are: memory technologies, allocation of functions among hardware and software, contending computer technologies for software implementation, and buffer design. The choices in software versus hardware implementations revolves around the various satellite channel to international channel mappings the unit must perform, and around the overload channel processing. Single card and single chip computers are shown to be useful tools in the design. Because of the interpolated nature of DSI operation, the design of a DSI unit is in a sense incomplete without an accompanying traffic simulator to verify performance. This unit performs the task of providing tests signals which contend for channels on a statistical basis.

Pseudo-error detectors are devices which show great potential for the measurement of the bit error rate of an on-line digital communications link. They are implemented in the form of a second detector (in addition and in parallel to the traffic data bit detector) which is very perturbation-sensitive. They do not compromise the traffic handling capacity of the system. Four methods of generating the pseudo-error characteristic are described: i) shifted detection threshold; ii) intersymbol interference enhancement; iii) noise addition; iv) sampling phase offset. Practical considerations generally govern the choice of method. Experimental results of pseudo-error detector behavior in the presence of Gaussian noise show that stable characteristics can be achieved to estimate a wide range of bit error rate (BER's) in very modest time intervals. In addition, experimental results in a real complex environment consisting of a 1.544 Mbits/s T1 capacity digital link using QPSK modulation techniques, including both Gaussian and non-Gaussian perturbations, show pseudo-error detection to be reliable for the measurement of BER and for controlling channel switching.