Common VR headsets require lenses that increase the field of view and allow the user to focus the display. In most systems, thick lenses are used that generate strong pincushion distortions. To account for this, the content is warped by a corresponding barrel distortion before displaying, resulting in undistorted images for the viewer. This approach assumes that the eye is exactly positioned, typically on the optical axis of the lens. However, in real systems the eye's location deviates from this optimal position even at rest; moreover, the pupil - and thus the optical center of the eye - moves by several millimeters when the user looks around. Thus, eye movement results in additional distortion, which is ignored in current VR headsets. Also in literature on head-mounted displays, the effect is most often not considered, or at least badly documented. The contribution of this paper are experiments that emphasize the importance of this mostly ignored effect. To this end, we have built a simple setup with a camera at variable eye positions in a standard VR headset, that allows us to directly measure the variation of distortion during eye movement. Our experiments show that distortion varies by several dozens of pixels within the full range of eye movements, which emphasizes that the effect is definitely significant. We also demonstrate how in a headset with built-in eye tracker, the knowledge of the eye position can be used to achieve a view-dependent lens correction with only minimal additional effort at run-time.

The paper proposes an architecture for a multiplier-adder network that can be used for the design of a digital neuron cell. The core of the multiplier is based on a hybrid memristor network, in which digital CMOS logic is combined with multi-stable storing memristor devices. The multi-bit storing feature of memristors is favoured since it simplifies the realisation of ternary data. Using such a ternary number system in binary logic leads to a redundant number representation (RNR) that allows to speed up multiplications since they are reduced to adders working in constant time independent of the word length. For the verification of the multiplier architecture an own special simulation system was developed in C++ allowing flexible design and fast analogue simulation of large complex memristor networks. The superiority of the hybrid memristive architecture in terms of latency and bandwidth compared to an adder with carry-look-ahead technique is analytically shown.