This paper presents a novel and powerful methodology for extracting functional blocks in hardware security and Trojan detection applications. The method is based on our proposed tester-based optical methodology that combines different test patterns, time-integrated and time-resolved emission measurements to identify and localize logic state changes and functional block activity inside a chip in a non invasive fashion. Detailed examples using a mixed-signal chip are presented and discussed to explain our proposed method.

Over the last decade, SiGe HBT BiCIMOS technology has matured from a laboratory research effort to become a 50/65-GHz fT/fmax silicon-based 0.5-/spl mu/m BiCMOS production technology. This progress has extended silicon-based production technology into the multigigahertz (multi-GHz) and multigigabits-per-second (multi-Gb/s) range, thus, opening up an array of wireless and wired circuit and network applications and markets. SiGe circuits are now being designed in the same application space as GaAs MESFET and HBTs, and offer the yield cost, stability and manufacturing advantages associated with conventional silicon fabrication. A wide range of microwave circuits have been built in this technology including 5.8-GHz low-noise amplifiers with 1-V supply, up to 17-GHz fully monolithic VCOs with excellent figures of merit, high-efficiency 2.4-GHz power devices with supply voltage of 1.5 V, and move complicated functions such as 2.5/5.0-GHz frequency synthesizer circuits as well as 10/12.5-Gb/s clock and data recovery PLLs. This paper focuses on several key circuit applications of SiGe BiCMOS technology and describes the performance improvements that can be obtained by its utilization in mixed-signal microwave circuit design. By way of examples, the article highlights the fact that the combination of high-bandwidth, high-gain and low-noise SiGe HBTs with dense CMOS functionality in a SiGe BiCMOS technology enables implementation of powerful single-chip transceiver architectures for multi-GHz and multi-Gb/s communication applications.

A fully monolithic phase-frequency locked loop (PFLL) for timing recovery applications is implemented in a 0.25 /spl mu/m digital CMOS technology. The circuit uses a digital phase-frequency detector (PFD) which provides a wide frequency acquisition capability with NRZ data inputs. An on-chip charge-pump loop filter is used to minimize jitter. The total power consumption is 250 mW from 2.5 V at 1.6 Gb/s.