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Giedrius Majauskas

dblp:17/2973 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 75% Integrated circuit design · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › design management
design reuse
0.012003
Application of design patterns for hardware design · DAC 2003
Electronic design automation › system-level design › communication synthesis
interface synthesis
0.012003
Application of design patterns for hardware design · DAC 2003
Electronic design automation › system-level design
IP integration
0.012003
Application of design patterns for hardware design · DAC 2003
Integrated circuit design › system-on-chip
system-on-chip design
0.012003
Application of design patterns for hardware design · DAC 2003

Methods — techniques the papers use, named apart from their topics

wrapper pattern · 0.0meta-programming · 0.0design patterns · 0.0
YearPublicationVenuePosition
2003 Application of design patterns for hardware design
abstract
Design patterns, which encapsulate common solutions to the recurring design problems, have contributed to the increased reuse, quality and productivity in software design. We argue that hardware design patterns could be used for customizing and integrating the Intellectual Property (IP) components into System-on-Chip designs. We formulate the role of design patterns in HW design, and describe their implementation using metaprogramming. We propose a Wrapper design pattern for adapting the behavior of the soft IPs, and demonstrate its application to the communication interface synthesis.
Robertas Damasevicius, Giedrius Majauskas, Vytautas Stuikys
DAC2
2001 Two approaches for developing generic components in VHDL
abstract
We consider the one- and two-language approaches (1LA & 2LA) for developing generic components (GCs) for VHDL generators. By 1LA & 2LA we mean a generalization using "pure" VHDL, or using the VHDL abstractions mixed with Open PROMOL, the external scripting language we have developed for building GCs and generators, respectively. We present the evaluation of both approaches.
Vytautas Stuikys, Giedrius Ziberkas, Robertas Damasevicius, Giedrius Majauskas
DATE4