Demo Data from SIGIR 2026 / reviewers in the wild / expert
Akhilesh Singhania
dblp:17/3909
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2009
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 2Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Parallel and multicore computing · 33% Embedded and real-time systems · 32% Memory systems · 25% | |
| Network and information security
1 paper |
Systems and software security · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 100% |
Topics — the 5 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Systems and software security
memory protection |
0.1 | 1 | 2007 | A System For Coarse Grained Memory Protection In Tiny Embedded Processors · DAC 2007 |
Systems and software security
memory safety |
0.1 | 1 | 2007 | A System For Coarse Grained Memory Protection In Tiny Embedded Processors · DAC 2007 |
Embedded and real-time systems
embedded processor |
0.1 | 1 | 2007 | A System For Coarse Grained Memory Protection In Tiny Embedded Processors · DAC 2007 |
Memory systems
memory protection |
0.1 | 1 | 2007 | A System For Coarse Grained Memory Protection In Tiny Embedded Processors · DAC 2007 |
Embedded and real-time systems › embedded software engineering › embedded software development
microcontroller deployment |
0.0 | 1 | 2007 | A System For Coarse Grained Memory Protection In Tiny Embedded Processors · DAC 2007 |
Methods — techniques the papers use, named apart from their topics
message passing · 0.2safe stack · 0.1jump table · 0.1hardware accelerators · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2009 | Your computer is already a distributed system. Why isn't your OS?
Andrew Baumann, Simon Peter 0001, Adrian Schüpbach, Akhilesh Singhania, Timothy Roscoe, Paul Barham 0001, Rebecca Isaacs |
HotOS | 4 |
| 2009 | The multikernel: a new OS architecture for scalable multicore systemsabstractCommodity computer systems contain more and more processor cores and exhibit increasingly diverse architectural tradeoffs, including memory hierarchies, interconnects, instruction sets and variants, and IO configurations. Previous high-performance computing systems have scaled in specific cases, but the dynamic nature of modern client and server workloads, coupled with the impossibility of statically optimizing an OS for all workloads and hardware variants pose serious challenges for operating system structures. Andrew Baumann, Paul Barham 0001, Pierre-Évariste Dagand, Tim Harris 0001, Rebecca Isaacs, Simon Peter 0001, Timothy Roscoe, Adrian Schüpbach, Akhilesh Singhania |
SOSP | 9 |
| 2007 | A System For Coarse Grained Memory Protection In Tiny Embedded ProcessorsabstractMany embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no form of memory protection. Programming errors in one application can easily corrupt the state of the operating system and other applications on the microcontroller. In this paper we propose a system that provides memory protection in tiny embedded processors. Our system consists of a software run-time working with minimal low-cost architectural extensions to the processor core that prevents corruption of state by buggy applications. We restrict memory accesses and control flow of applications to protection domains within the address space. The software run-time consists of a Memory map: a flexible and efficient data structure that records ownership and layout information of the entire address space. Memory map checks are done for store instructions by hardware accelerators that significantly improve the performance of our system. We preserve control flow integrity by maintaining a Safe stack that stores return addresses in a protected memory region. Cross domain function calls are redirected through a software based jump table. Enhancements to the microcontroller call and return instructions use the jump table to track the current active domain. We have implemented our scheme on a VHDL model of ATMEGA103 microcontroller. Our evaluations show that embedded applications can enjoy the benefits of memory protection with minimal impact on performance and a modest increase in the area of the microcontroller. Ram Kumar 0001, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani Srivastava 0001 |
DAC | 2 |