Demo Data from SIGIR 2026 / reviewers in the wild / expert
Tatsuya Shimoda
dblp:17/3990
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2002
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 67% Electronic design automation · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
circuit simulation |
0.0 | 1 | 2002 | Table look-up model of thin-film transistors for circuit simulationusing spline interpolation with transformation by y=x+log(x) · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Integrated circuit design › analog and mixed-signal circuits
device modeling |
0.0 | 1 | 2002 | Table look-up model of thin-film transistors for circuit simulationusing spline interpolation with transformation by y=x+log(x) · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Integrated circuit design › semiconductor device modeling
thin-film transistor modeling |
0.0 | 1 | 2002 | Table look-up model of thin-film transistors for circuit simulationusing spline interpolation with transformation by y=x+log(x) · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Methods — techniques the papers use, named apart from their topics
table look-up model · 0.0spline interpolation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2002 | Table look-up model of thin-film transistors for circuit simulationusing spline interpolation with transformation by y=x+log(x)abstractA table look-up model of thin-film transistors has been developed for circuit simulation. This model utilizes three schemes. First, the spline interpolation with transformation by y = x+log(x) achieves precision for both on-current and off-current simultaneously. Second, the square polynomial supplement solves an anomaly near the points where drain voltage equals zero. Third, the linear extrapolation achieves continuities of the current and its derivatives as a function of voltages for areas outside where the spline interpolation is performed and improves convergence during circuit simulation. Mutsumi Kimura, Satoshi Inoue, Tatsuya Shimoda |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |