Routability or wiring congestion in a very large scale integration chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield, and chip area. Although advances in placement algorithms have attempted to alleviate this problem, the inherent structure of the logic netlist has a significant impact on the routability irrespective of the placement algorithm used. Placement algorithms find optimal assignments of locations to the logic and do not have the ability to change the netlist structure. Significant decisions regarding the circuit structure are made early in synthesis during the technology-independent logic-optimization step. Optimizations in this step use literal count as a metric for optimization and do not adequately capture the intrinsic entanglement of the netlist. Two circuits with identical literal counts may have significantly different congestion characteristics after placement. In this paper, we postulate that a property of the network structure called adhesion can make a significant contribution to routing congestion. We then provide a metric to measure this property. We evaluate the utility of adhesion as measured by this metric to estimate and optimize postrouting congestion early in the design flow. A heuristic for measuring adhesion is evaluated as well.

Routability or wiring congestion in a VLSI chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield and chip area. Although advances in placement algorithms have attempted to alleviate this problem, the inherent structure of the logic netlist has a significant impact on the routability irrespective of the placement algorithm used. Placement algorithms find optimal assignment of locations to the logic and do not have the ability to change the netlist structure. Significant decisions regarding the circuit structure are made early in synthesis such as during the technology independent logic optimization step. Optimizations in this step use literal count as a metric for optimization and do not adequately capture the intrinsic entanglement of the netlist. Two circuits with identical literal counts may have significantly different congestion characteristics post placement. In this paper, we motivate that a property of the network structure called adhesion can make a significant contribution to routing congestion. We then provide a metric to measure this property. We also show that adhesion as measured by this metric can be used in addition to literal counts to estimate and optimize post routing congestion early in the design flow.

Our methodology unifies behavioral synthesis and physical design, allowing scheduling, allocation, binding, and placement to occur simultaneously. This is accomplished via set of defined transformation from both domains acting as forces in a single behavioral/physical system. Experiments show results with 50% less area and 10% lower critical path delay than the best results from a commercial behavioral synthesis tool. Our behavioral level area, delay, and individual component location estimates closely match results produced by physical design tools given only pin locations as a starting point.

While guarded evaluation has proven an effective energy saving technique in arithmetic circuits, good methodologies do not exist for determining when and how to guard for maximal savings.Three new internal guarding techniques are presented in adders that increase energy savings up to 38% over existing external guarding techniques.This allows guarded evaluation to be effective at duty cycles as much as 20% higher than are currently practical.A modeling methodology is presented defining the energy and energy delay of a unit in a generic application space.These models can easily be incorporated into an automated selection technique to determine the optimal guarded implementation.This technique is tested on a DSP ASIP, increasing overall energy savings by preventing unnecessary guarding.The data is generalized and it is observed that guarding is most beneficial when the ratio of guarding transistors to driven computational transistors is 'Ilo or lower.

Genetic algorithms have proven to be a viable solution to the NP-complete problem of test vector generation. However the parameters used to control GA-based ATPG can greatly affect test set size, fault coverage and CPU execution time. Knowing how a given set of parameters will affect each of these factors a priori allows for more efficient testing procedures. Over 1 million ATPG experiments were conducted on the ISCAS85 benchmark set exploring a wide range of parameter options. Although sequential circuit testing looms as the larger problem, investigating combinational circuits should provide direction as to where efforts should be focused. From our experiments, we derive regression-based equations utilizing circuit characteristics and various controllable parameters. Using these equations, the ATPG tool determines parameter values that maximize fault coverage while meeting constraints on CPU run times and test set size. For many circuits tested, fault coverage improved with a tolerable increase in CPU time.