Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Hany Ragab

dblp:171/1877 · DBLP profile ↗
← Back
5ranked-venue papers
3as first author
4since 2021 · last 2025
0000-0003-2645-7423ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 5 · 3 first-author · 4 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
4 papers
Hardware security and side channels · 80% Privacy and data protection · 20%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 92% Processor architecture and microarchitecture · 8%
Software engineering, system software, and programming languages
1 paper
Concurrent programming · 100%

Topics — the 8 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › microarchitectural attacks
transient execution attack
2.642025
Phantom Trails: Practical Pre-Silicon Discovery of Transient Data Leaks · USENIX Security Symposium 2025
GhostRace: Exploiting and Mitigating Speculative Race Conditions · USENIX Security Symposium 2024
Rage Against the Machine Clear: A Systematic Analysis of Machine Clears and Their Implications for Transient Execution Attacks · USENIX Security Symposium 2021
Privacy and data protection › information leakage
data leakage detection
0.912025
Phantom Trails: Practical Pre-Silicon Discovery of Transient Data Leaks · USENIX Security Symposium 2025
Electronic design automation
hardware verification and test
0.912025
Phantom Trails: Practical Pre-Silicon Discovery of Transient Data Leaks · USENIX Security Symposium 2025
Electronic design automation › hardware verification and test › functional verification
pre-silicon verification
0.912025
Phantom Trails: Practical Pre-Silicon Discovery of Transient Data Leaks · USENIX Security Symposium 2025
Concurrent programming
memory models
0.212024
GhostRace: Exploiting and Mitigating Speculative Race Conditions · USENIX Security Symposium 2024
Hardware security and side channels › trusted execution environments
SGX enclave
0.112021
CrossTalk: Speculative Data Leaks Across Cores Are Real · SP 2021
Hardware security and side channels
trusted execution environments
0.112021
CrossTalk: Speculative Data Leaks Across Cores Are Real · SP 2021
Processor architecture and microarchitecture
speculative execution
0.112021
Rage Against the Machine Clear: A Systematic Analysis of Machine Clears and Their Implications for Transient Execution Attacks · USENIX Security Symposium 2021

Methods — techniques the papers use, named apart from their topics

information flow tracking · 1.7performance counter profiling · 0.5
YearPublicationVenuePosition
2025 Phantom Trails: Practical Pre-Silicon Discovery of Transient Data Leaks
Alvise de Faveri Tron, Raphael Isemann, Hany Ragab, Cristiano Giuffrida, Klaus von Gleissenthall, Herbert Bos
USENIX Security Symposium3
2024 GhostRace: Exploiting and Mitigating Speculative Race Conditions
Hany Ragab, Andrea Mambretti, Anil Kurmus, Cristiano Giuffrida
USENIX Security Symposium1
2021 CrossTalk: Speculative Data Leaks Across Cores Are Real
abstract
Recent transient execution attacks have demonstrated that attackers may leak sensitive information across security boundaries on a shared CPU core. Up until now, it seemed possible to prevent this by isolating potential victims and attackers on separate cores. In this paper, we show that the situation is more serious, as transient execution attacks can leak data across different cores on many modern Intel CPUs.We do so by investigating the behavior of x86 instructions, and in particular, we focus on complex microcoded instructions which perform offcore requests. Combined with transient execution vulnerabilities such as Micro-architectural Data Sampling (MDS), these operations can reveal internal CPU state. Using performance counters, we build a profiler, CROSSTALK, to examine the number and nature of such operations for many x86 instructions, and find that some instructions read data from a staging buffer which is shared between all CPU cores.To demonstrate the security impact of this behavior, we present the first cross-core attack using transient execution, showing that even the seemingly-innocuous CPUID instruction can be used by attackers to sample the entire staging buffer containing sensitive data – most importantly, output from the hardware random number generator (RNG) – across cores. We show that this can be exploited in practice to attack SGX enclaves running on a completely different core, where an attacker can control leakage using practical performance degradation attacks, and demonstrate that we can successfully determine enclave private keys. Since existing mitigations which rely on spatial or temporal partitioning are largely ineffective to prevent our proposed attack, we also discuss potential new mitigation techniques.
Hany Ragab, Alyssa Milburn, Kaveh Razavi, Herbert Bos, Cristiano Giuffrida
SP1
2021 Rage Against the Machine Clear: A Systematic Analysis of Machine Clears and Their Implications for Transient Execution Attacks
Hany Ragab, Enrico Barberis, Herbert Bos, Cristiano Giuffrida
USENIX Security Symposium1
2015 On the Weaknesses of PBKDF2
Andrea Visconti, Simone Bossi, Hany Ragab, Alexandro Calò
CANS3