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Webb Horn

dblp:173/9801 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2015
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 67% Parallel and multicore computing · 33%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache coherence
0.212015
Exploiting commutativity to reduce the cost of updates to shared data in cache-coherent systems · MICRO 2015
Memory systems › cache coherence
coherence protocol optimization
0.212015
Exploiting commutativity to reduce the cost of updates to shared data in cache-coherent systems · MICRO 2015

Methods — techniques the papers use, named apart from their topics

update-only permission · 0.2partial update coalescing · 0.2
YearPublicationVenuePosition
2015 Exploiting commutativity to reduce the cost of updates to shared data in cache-coherent systems
abstract
We present Coup, a technique to lower the cost of updates to shared data in cache-coherent systems. Coup exploits the insight that many update operations, such as additions and bitwise logical operations, are commutative: they produce the same final result regardless of the order they are performed in. Coup allows multiple private caches to simultaneously hold update-only permission to the same cache line. Caches with update-only permission can locally buffer and coalesce updates to the line, but cannot satisfy read requests. Upon a read request, Coup reduces the partial updates buffered in private caches to produce the final value. Coup integrates seamlessly into existing coherence protocols, requires inexpensive hardware, and does not affect the memory consistency model.
Guowei Zhang 0002, Webb Horn, Daniel Sánchez 0003
MICRO2