The Internet of Things (IoT) with its plethora of applications brings up new challenges in optimizing power consumption, error performance, latency, and throughput in its communication devices. Recently, there has been increasing necessity of reconfigurable and multistandard transceivers in order to bring adaptability in the IoT devices to suit the nature of the application and satisfy the aforementioned performance metrics as well. In this paper, we focus on the efficient design of receivers compliant with IEEE 802.15.4 which is a prominent protocol for low power IoT applications. We propose a robust phase noise compensation method which efficiently removes the residual phase noise remaining after the coarse frequency offset compensation due to direct-sequence spread spectrum operation on large packets. We also propose a dual-mode receiver using the proposed compensation method and showcase its ability to cater to the diverse nature of IoT applications. The detailed architecture of proposed dual-mode receiver is presented along with its FPGA prototyping and ASIC implementation. We have analyzed overall power consumption by the proposed dual-mode receiver considering the packet error rate and retransmission scenario. The results show that the proposed receiver saves significant energy consumption by changing its mode in favorable channel environments.

With the proliferation of Internet of Things (IoT), the IEEE 802.15.4 physical layer is becoming increasingly popular due to its low power consumption. However, secure data communication over the network is a challenging issue because vulnerabilities in the existing security primitives lead to several attacks. The mitigation of these attacks separately adds significant computing burden on the legitimate node. In this paper, we propose a secure IEEE 802.15.4 transceiver design that mitigates multiple attacks simultaneously by using a physical layer encryption approach that reduces the computations at the upper layers. In addition to providing confidentiality and integrity services, the proposed transceiver provides sufficient complexity to various attacks, such as cryptanalysis and traffic analysis attacks. It also significantly improves the lifetime of the node in the presence of a ghost attacker by preventing the legitimate node from processing the bogus messages and hence combats against energy depletion attacks. The simulation results show that a high symbol error rate at the adversary can be achieved using the proposed transceiver without affecting the throughput at the legitimate node. In this paper, we also analyze the hardware complexity by developing an FPGA and ASIC prototype of the proposed transceiver.