Conventional Simulated Annealing (SA) based placement methods for FPGAs generate high quality results in terms of wirelength and critical path delay, but at a high runtime cost. In case of modern multi-million gate FPGAs, SA-based methods for placement take a large portion of runtime in the FPGA CAD flow. In this paper, we propose a fast and efficient timing driven open-source analytical placement engine targeted at global placement for FPGAs followed by low temperature SA for detailed placement. Our global placement engine uses quadratic programming to minimize wirelength and employs dynamic net weights based on timing criticality between the nets to minimize the critical path delay iteratively. Experimental results show, on average, a 30% runtime improvement for our proposed global placer compared to VPR placer while having approximately the same critical path delay at an expense of 3% larger overall wirelength and channel width after routing with 20 largest MCNC benchmark circuits. The runtime improvement is seen despite the fact that our global placement engine is currently implemented in MATLAB. We expect our runtime to improve notably once we port the code to C. On combining the detailed placement runtime, our proposed approach performs faster for almost all the large circuits having more than 250 blocks. The results show that this placer performs faster global placement across all benchmarks, hence it is easily scalable with modern complex FPGA designs.