This paper proposes a highly parallelized architecture for a distributed queue dual bus (DQDB) MAC layer protocol processor, that is expected to improve the speed of execution of the protocol significantly to match the gigabit per second transmission rates. The architecture is based on pipelines of service blocks operating in parallel. Also the receive and transmit functions are separated and parallelized. Thus, basically, the isochronous, connection-oriented and MAC services are defined as three parallel blocks, each consisting of parallel receive and send functions. Fundamental to the architecture are multiport global receive and send memories which allow manipulation of separate data units in parallel without having to physically transfer data between different service stages. Each service block is divided into parallel subblocks, thereby exploiting the possibility of parallelism and pipelining as much as possible.>