Demo Data from SIGIR 2026 / reviewers in the wild / expert
Kenneth W. Sussman
dblp:178/9181
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1968
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 33% Integrated circuit design · 33% Performance modeling and evaluation · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › analog and mixed-signal circuits
analog circuit design |
0.0 | 1 | 1968 | The Separation Technique: A Method for Simulating Transistors to Aid Integrated Circuit Design · IEEE Trans. Computers 1968 |
Performance modeling and evaluation › simulation › analog and hybrid computer simulation
analog computer simulation |
0.0 | 1 | 1968 | The Separation Technique: A Method for Simulating Transistors to Aid Integrated Circuit Design · IEEE Trans. Computers 1968 |
Electronic design automation
circuit simulation |
0.0 | 1 | 1968 | The Separation Technique: A Method for Simulating Transistors to Aid Integrated Circuit Design · IEEE Trans. Computers 1968 |
Methods — techniques the papers use, named apart from their topics
time scaling · 0.0separation technique · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1968 | The Separation Technique: A Method for Simulating Transistors to Aid Integrated Circuit DesignabstractAbstract—A new technique that uses the transistor itself as a computing element has been developed for simulating transistors on the analog computer. The method is called the separation technique since it separates the high-and low-frequency behavior of the simulated transistor. The high-frequency behavior of the transistor is time scaled by a factor (typically one million) suitable for computer simulation. E. James Angelo Jr., John Logan, Kenneth W. Sussman |
IEEE Trans. Computers | 3 |