Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Muhammad Teguh Satria

dblp:179/2957 · DBLP profile ↗
← Back
2ranked-venue papers
1as first author
0since 2021 · last 2016
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 44% GPUs and heterogeneous computing · 44% Processor architecture and microarchitecture · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing
control flow divergence
0.212016
An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016
Performance modeling and evaluation › processor performance modeling › accelerator performance modeling
GPU performance modeling
0.212016
An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016
Processor architecture and microarchitecture
SIMD
0.112016
An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016

Methods — techniques the papers use, named apart from their topics

thread regrouping · 0.2runtime transformation · 0.2compile-time analysis · 0.2
YearPublicationVenuePosition
2016 Real-time system-level implementation of a telepresence robot using an embedded GPU platform
Muhammad Teguh Satria, Swathi T. Gurumani, Keng Peng Tee, Augustine Koh, Pan Yu, Kyle Rupnow, Deming Chen
DATE1
2016 An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization
abstract
Graphic processing units (GPUs) are composed of a group of single-instruction multiple data (SIMD) streaming multiprocessors (SMs). GPUs are able to efficiently execute highly data parallel tasks through SIMD execution on the SMs. However, if those threads take diverging control paths, all divergent paths are executed serially. In the worst case, every thread takes a different control path and the highly parallel architecture is used serially by each thread. This control flow divergence problem is well known in GPU development; code transformation, memory access redirection, and data layout reorganization are commonly used to reduce the impact of divergence. These techniques attempt to eliminate divergence by grouping together threads or data to ensure identical behavior. However, prior efforts using these techniques do not model the performance impact of any particular divergence or consider that complete elimination of divergence may not be possible. Thus, we perform analysis of the performance impact of divergence and potential thread regrouping algorithms that eliminate divergence or minimize the impact of remaining divergence. Finally, we develop a divergence optimization framework that analyzes and transforms the kernel at compile-time and regroups the threads at runtime. For the compute-bound applications, our proposed metrics achieve performance estimation accuracy within 6.2% of measured performance. Using these metrics, we develop thread regrouping algorithms, which consider the impact of divergence, and speed up these applications by 2.2× on average on NVIDIA GTX480.
Yun Liang 0001, Muhammad Teguh Satria, Kyle Rupnow, Deming Chen
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2