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Glenn David Bergland

dblp:179/4943 · DBLP profile ↗
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6ranked-venue papers
6as first author
0since 2021 · last 1986
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-authorComputer networks · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Electronic design automation · 48% Hardware accelerators and domain-specific architectures · 16% Distributed systems · 15%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
design methodology
0.011978
Structured design methodologies · DAC 1978
Electronic design automation › design methodology
structured design methodologies
0.011978
Structured design methodologies · DAC 1978
Hardware accelerators and domain-specific architectures
signal processing accelerator
0.021972
A Parallel Implementation of the Fast Fourier Transform Algorithm · IEEE Trans. Computers 1972
Digital Real-Time Spectral Analysis · IEEE Trans. Electron. Comput. 1967
Parallel and multicore computing
parallel algorithms
0.011972
A Parallel Implementation of the Fast Fourier Transform Algorithm · IEEE Trans. Computers 1972
High-performance computing › fast fourier transform
parallel FFT
0.011972
A Parallel Implementation of the Fast Fourier Transform Algorithm · IEEE Trans. Computers 1972

Methods — techniques the papers use, named apart from their topics

parallel element processing ensemble · 0.0fast fourier transform · 0.0cooley-tukey algorithm · 0.0
YearPublicationVenuePosition
1986 Guest Editor's Prologue Special Issue on Software Design Methods
abstract
We describe why these papers were chosen, and categorize them in terms of major contribution, underlying model of the software life-cycle, and applicability to various types of system.
Glenn David Bergland, Pamela Zave
IEEE Trans. Software Eng.1
1983 An Experimental Telecommunications Test Bed
abstract
Although the computer and telecommunications industries have traditionally represented two very different cultures, recent advances in circuit and system technology have blurred many of their past distinctions. A digital system test bed environment has been implemented that not only supports but encourages the use of terminal, switching, and processing capabilities for both computing and communicating. One of our major goals was to provide a test bed environment for conducting telecommunications terminal (teleterminal) experiments in the context of work, school, home, and play. Model scenarios for each environment are briefly described. Physically, the experimental environment is a blend of model shop and commercial systems and components. Adaptability and versatility have been given higher priority than manufacturability. The testing of concepts is deemed more relevant than the testing of components. The resulting environment does not model all of the application areas but has provided a wealth of illustrative data and insights that are described in companion papers.
Glenn David Bergland
IEEE J. Sel. Areas Commun.1
1982 Guest Editors' Prologue-Scanning the Issue
abstract
Many of the papers presented in this Special Issue address difficult issues of designing communications software. While no attempt at completeness has been attempted, we do feel that the papers selected deal with timely and relevant issues which communications professionals should be familiar with. This Special Issue consists of five major sections: software methodology, CCITT programming languages, software tools, switching software architectures, and communications software for computers. Since this is the first Special Issue on Communications Software we feel that it may be useful to give a rather detailed overview of each section to introduce the readers not familiar with the area to the exciting world of Communications Software. We have attempted to summarize the highlights of each paper in this prologue.
Glenn David Bergland, Roger C. Cheung
IEEE Trans. Commun.1
1978 Structured design methodologies
Glenn David Bergland
DAC1
1972 A Parallel Implementation of the Fast Fourier Transform Algorithm
abstract
For many real-time signal processing problems, correlations, convolutions, and Fourier analysis must be performed in special-purpose digital hardware. At relatively high levels of performance, it becomes necessary for this hardware to perform some of its computations in parallel. A parallel FFT algorithm is described that segments the fast Fourier transform algorithm into groups of identical parallel operations that can be performed concurrently and independently. A hardware implementation of the algorithm is described in the context of the parallel element processing ensemble (PEPE) previously described by Githens [7], [8].
Glenn David Bergland
IEEE Trans. Computers1
1967 Digital Real-Time Spectral Analysis
abstract
The fast Fourier transform algorithm, reported by Cooley and Tukey, results in substantial computational savings and permits a considerable amount of parallel computation. By making use of these features, estimates of the spectral components of a time function can be calculated by a special-purpose digital machine while the function is being sampled. In this paper, two digital machine organizations are suggested which use the algorithm for the case of N (the number of samples analyzed) being a power of 2 and the case of N being the product of two integers. The first machine consists of shift registers and arithmetic units organized in stages which perform calculations in parallel. It can be used when N is a power of 2 and can accept signals being sampled at a rate exceeding 500 000 samples per second. The second machine requires fewer shift registers and only one arithmetic unit but cannot operate in a continuous manner. This means that either a dead time between adjacent records of data must be allowed or a time compression unit must be used. In the first case the obtainable sampling rate depends upon the dead time which can be allowed between adjacent records of data. In the second case sampling rates up to 8000 samples per second are feasible. For this analyzer, N is required to be expressible as the product of two integers.
Glenn David Bergland, Harry W. Hale
IEEE Trans. Electron. Comput.1