Improving routability during both global and detailed routing stage has become a critical problem in modern VLSI design. In this work, we propose a placement framework that offers a complete coverage solution in considering both global and detailed routing congestion. A placement migration strategy is proposed, which improves detailed routing congestion while preserving the placement integrity that is optimized for global routability. Using the benchmarks released from ISPD2014 Contest, practical design rules in advanced node design are considered in our placement framework. Evaluation on routability of our placement framework is conducted using commercial router provided by the 2014 ISPD Contest organizers. Experimental results show that the proposed methodologies can effectively improve placement solutions for both global and detailed router.

This work tackles a problem of clock power minimization within a skew constraint under supply voltage variation. This problem is defined in the ISPD 2010 benchmark. Unlike mesh and cross link that reduce clock skew uncertainty by multiple driving paths, our focus is on controlling skew uncertainty in the structure of the tree. We observe that slow slew amplifies supply voltage variation, which induces larger path delay variation and skew uncertainty. To obtain the optimality, we formulate a symmetric clock tree synthesis as a mathematical programming problem in which the slew effect is considered by an NLDM-like cell delay variation model. A symmetry-to-asymmetry tree transformation is proposed to further reduce wire loading. Experimental results show that the proposed four methods save up to 20% of clock tree capacitance loading. Beyond controlling slew to suppress supply-voltage-variation-induced skew, we also discuss the strategies of clock tree synthesis under variant variation scenarios and the limitations of the ISPD 2010 benchmark.

Clock skew resulted by process variation becomes more and more serious as technology shrinks. In 2010, ISPD held a high performance clock network synthesis contest; it considered supply-voltage variation and wire manufacturing variation. Previous works show that the main issue of variation induced skew is on supply-voltage variation. To trade off power and supply-voltage variation induced skew more effectively, we adapt a tree topology which use a timing model independent symmetrical tree at top level to drive the bottom level non-symmetry trees. Our method gives top tree more power budget to reduce supply-voltage variation induced skew and greedily saves power consuming in bottom level. Experimental results are evaluated from the benchmarks of ISPD contest 2010. Compared with state-of-the-art cross link work, the proposed technique reduces 10% of power consumption on average and also improves the run time.

A monolithic CMOS MEMS capacitive accelerometer with micropower analog readout circuit is presented in this paper. In order to optimize noise-power performance of accelerometer in limited area, a specification driven MEMS/IC co-design flow is adopted. In analog readout circuit design, the proposed circuit architecture combines chopper stabilization and correlated double sampling to suppress low frequency noise and compensate DC offset. The RMS input referred noise voltage is 9.82 nV/√Hz under 100Hz. The power consumption is 36uW at 100kHz modulation frequency.

The purpose of this research is to design an automatic beam-switching array for ATSC DTV reception. Such an antenna system is potentially applied on a moving vehicle for the mobile reception. Four wideband and directional horn antennas form this array. Several techniques are presented to gain those wideband and directional characteristics, including an L-slot design on the horn and optimal dimensional design for the feeding probe inside the horn. A circuit is designed to play the role of selection hardware, by which only the strongest incoming wave is chosen in a multi-path environment. Real receiving test was performed inside a basement as well.

Detection of moving objects is an important research topic in visual tracking applications. Among the moving object detection algorithms, the background subtraction based method is widely adopted due to advantages such as less computational load and high detection quality. However, it is sensitive to illumination changes and fluctuating backgrounds. Moreover, it cannot deal with slow moving and temporarily stationary objects. Although numerous works concerning background model initialization and adaptation have reportedly overcome the obstacles associated with illumination changes and fluctuating backgrounds, however detection of slow moving and temporarily stationary objects remains a challenging issue. Hence, this paper is aimed at developing a novel real-time motion detection algorithm that can deal with the aforementioned problem. Experimental results demonstrate the effectiveness of the proposed approach.