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J. J. Amodei

dblp:180/6304 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1964
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design › arithmetic circuit design
adder design		 0.011964
High-Speed Adders and Comparators Using Transistors and Tunnel Dioes · IEEE Trans. Electron. Comput. 1964
Integrated circuit design › digital circuit design
arithmetic circuit design		 0.011964
High-Speed Adders and Comparators Using Transistors and Tunnel Dioes · IEEE Trans. Electron. Comput. 1964
Integrated circuit design › digital circuit design › arithmetic circuit design
comparator circuit		 0.011964
High-Speed Adders and Comparators Using Transistors and Tunnel Dioes · IEEE Trans. Electron. Comput. 1964
Integrated circuit design
digital circuit design		 0.011964
High-Speed Adders and Comparators Using Transistors and Tunnel Dioes · IEEE Trans. Electron. Comput. 1964
Integrated circuit design › analog and mixed-signal circuits
tunnel diode circuit		 0.011964
High-Speed Adders and Comparators Using Transistors and Tunnel Dioes · IEEE Trans. Electron. Comput. 1964

Methods — techniques the papers use, named apart from their topics

tolerance analysis · 0.0switching analysis · 0.0
YearPublicationVenuePosition
1964 High-Speed Adders and Comparators Using Transistors and Tunnel Dioes
abstract
Comparators and adders are among the circuits that can take best advantage of the combined properties of transistors and tunnel diodes. The paper describes a transistor-tunnel diode complementary output pair module that is used as a basis for several configurations of comparators, half adder and full adder circuits. The comparators and half adders are discussed qualitatively. A detailed design and tolerance analysis of the full adder circuit is presented and the design equations that will optimize the tolerance requirements are derived. A switching analysis of the carry portion of the full adder circuit is carried out. The results illustrate that stray elements rather than intrinsic device performance are the dominant factors contributing to carry delay in a conventionally wired system. The paper also describes the results of the tests made on an eight-bit adder system which was constructed with conventionally encapsulated devices and standard wiring. The average carry delay per stage in this system was ¾ nsec. The time required to obtain the correct final sum output was 3 to 5 nsec after arrival of the carry. Tests with specially encapsulated high-speed transistors and low-capacity gallium arsenide tunnel diodes showed 0.2-nsec carry delay and 2-nsec sum delay.
J. J. Amodei
 IEEE Trans. Electron. Comput.1