Demo Data from SIGIR 2026 / reviewers in the wild / expert
Lucio Tavernini
dblp:180/6393
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1965
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Performance modeling and evaluation · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation › simulation
analog and hybrid computer simulation |
0.0 | 1 | 1965 | The Automatic Sequencing of Block-Operators in the Digital Simulation of Analog and Analog-Hybrid Computers · IEEE Trans. Electron. Comput. 1965 |
Performance modeling and evaluation
simulation |
0.0 | 1 | 1965 | The Automatic Sequencing of Block-Operators in the Digital Simulation of Analog and Analog-Hybrid Computers · IEEE Trans. Electron. Comput. 1965 |
Methods — techniques the papers use, named apart from their topics
graph algorithms · 0.0algebraic loop detection · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1965 | The Automatic Sequencing of Block-Operators in the Digital Simulation of Analog and Analog-Hybrid ComputersabstractThe all-digital simulation of analog or analog-hybrid systems requires that the processing sequence of the elements simulated be admissible in the sense that no element should be processed until the values of all of its input variables are known. This paper presents an algorithm to automatically ascertain an admissible processing sequence from a given interconnection configuration, and to automatically detect any algebraic loops contained therein. As a result, a parallel language, rather than a sequential one, may be used to write source programs for digital simulation. Lucio Tavernini |
IEEE Trans. Electron. Comput. | 1 |