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Binh Pham 0003

dblp:181/2751-3 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 2015
0000-0002-0336-3777ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Memory systems · 90% Cloud and datacenter computing · 10%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 13 heaviest of 13, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory management › virtual memory
address translation
0.632015
Large pages and lightweight memory management in virtualized environments: can you have it both ways? · MICRO 2015
Increasing TLB reach by exploiting clustering in page translations · HPCA 2014
CoLT: Coalesced Large-Reach TLBs · MICRO 2012
Memory systems › memory management
virtual memory
0.632015
Large pages and lightweight memory management in virtualized environments: can you have it both ways? · MICRO 2015
Increasing TLB reach by exploiting clustering in page translations · HPCA 2014
CoLT: Coalesced Large-Reach TLBs · MICRO 2012
Memory systems › memory management › virtual memory › address translation
TLB
0.432015
Large pages and lightweight memory management in virtualized environments: can you have it both ways? · MICRO 2015
CoLT: Coalesced Large-Reach TLBs · MICRO 2012
Increasing TLB reach by exploiting clustering in page translations · HPCA 2014
Memory systems › memory management › virtual memory
huge pages
0.212015
Large pages and lightweight memory management in virtualized environments: can you have it both ways? · MICRO 2015
Memory systems › memory management
memory deduplication
0.212015
Large pages and lightweight memory management in virtualized environments: can you have it both ways? · MICRO 2015
Memory systems
memory management
0.212015
Large pages and lightweight memory management in virtualized environments: can you have it both ways? · MICRO 2015
Cloud and datacenter computing
virtualization
0.212015
Large pages and lightweight memory management in virtualized environments: can you have it both ways? · MICRO 2015
Memory systems › memory management › virtual memory
TLB reach
0.212014
Increasing TLB reach by exploiting clustering in page translations · HPCA 2014
Memory systems › memory management › memory allocation
page allocation
0.112012
CoLT: Coalesced Large-Reach TLBs · MICRO 2012
Memory systems › virtual memory management
TLB coalescing
0.112012
CoLT: Coalesced Large-Reach TLBs · MICRO 2012
Cloud and datacenter computing › virtualization
virtual machine migration
0.112015
Large pages and lightweight memory management in virtualized environments: can you have it both ways? · MICRO 2015
Memory systems
cache
0.112014
Increasing TLB reach by exploiting clustering in page translations · HPCA 2014
Operating systems › resource management
memory management
0.012012
CoLT: Coalesced Large-Reach TLBs · MICRO 2012

Methods — techniques the papers use, named apart from their topics

real-system measurement · 0.3speculative translation grouping · 0.2workload characterization · 0.2
YearPublicationVenuePosition
2015 Large pages and lightweight memory management in virtualized environments: can you have it both ways?
abstract
Large pages have long been used to mitigate address translation overheads on big-memory systems, particularly in virtualized environments where TLB miss overheads are severe. We show, however, that far from being a panacea, large pages are used sparingly by modern virtualization software. This is because large pages often preclude lightweight memory management, which can outweigh their Translation Lookaside Buffer (TLB) benefits. For example, they reduce opportunities to deduplicate memory among virtual machines in overcommitted systems, interfere with lightweight memory monitoring, and hamper the agility of virtual machine (VM) migrations. While many of these problems are particularly severe in overcommitted systems with scarce memory resources, they can (and often do) exist generally in cloud deployments. In response, virtualization software often (though it doesn't have to) splinters guest operating system (OS) large pages into small system physical pages, sacrificing address translation performance for overall system-level benefits. We introduce simple hardware that bridges this fundamental conflict, using speculative techniques to group contiguous, aligned small page translations such that they approach the address translation performance of large pages. Our Generalized Large-page Utilization Enhancements (GLUE) allow system hypervisors to splinter large pages for agile memory management, while retaining almost all of the TLB performance of unsplintered large pages.
Binh Pham 0003, Ján Veselý, Gabriel H. Loh, Abhishek Bhattacharjee
MICRO1
2014 Increasing TLB reach by exploiting clustering in page translations
abstract
The steadily increasing sizes of main memory capacities require corresponding increases in the processor's translation lookaside buffer (TLB) resources to avoid performance bottlenecks. Large operating system page sizes can mitigate the bottleneck with a smaller TLB, but most OSs and applications do not fully utilize the large-page support in current hardware. Recent work has shown that, while not guaranteed, some virtual-to-physical page mappings exhibit “contiguous” spatial locality in which consecutive virtual pages map to consecutive physical pages. Such locality provides opportunities to coalesce “adjacent” TLB entries for increased reach. We observe that beyond simple adjacent-entry coalescing, many more translations exhibit “clustered” spatial locality in which a group or cluster of nearby virtual pages map to a similarly clustered set of physical pages. In this work, we provide a detailed characterization of the spatial locality among the virtual-to-physical translations. Based on this characterization, we present a multi-granular TLB organization that significantly increases its effective reach and reduces miss rates substantially while requiring no additional OS support. Our evaluation shows that the multi-granular design outperforms conventional TLBs and the recently proposed coalesced TLBs technique.
Binh Pham 0003, Abhishek Bhattacharjee, Yasuko Eckert, Gabriel H. Loh
HPCA1
2012 CoLT: Coalesced Large-Reach TLBs
abstract
Translation Look aside Buffers (TLBs) are critical to system performance, particularly as applications demand larger working sets and with the adoption of virtualization. Architectural support for super pages has previously been proposed to improve TLB performance. By allocating contiguous physical pages to contiguous virtual pages, the operating system (OS) constructs super pages which need just one TLB entry rather than the hundreds required for the constituent base pages. While this greatly reduces TLB misses, these gains are often offset by the implementation difficulties of generating and managing ample contiguity for super pages. We show, however, that basic OS memory allocation mechanisms such as buddy allocators and memory compaction naturally assign contiguous physical pages to contiguous virtual pages. Our real-system experiments show that while usually insufficient for super pages, these intermediate levels of contiguity exist under various system conditions and even under high load. In response, we propose Coalesced Large-Reach TLBs (CoLT), which leverage this intermediate contiguity to coalesce multiple virtual-to-physical page translations into single TLB entries. We show that CoLT implementations eliminate 40\% to 58\% of TLB misses on average, improving performance by 14\%. Overall, we demonstrate that the OS naturally generates page allocation contiguity. CoLT exploits this contiguity to eliminate TLB misses for next-generation, big-data applications with low-overhead implementations.
Binh Pham 0003, Viswanathan Vaidyanathan, Aamer Jaleel, Abhishek Bhattacharjee
MICRO1