Computing-in-Memory (CIM) architecture effectively reduces power consumption caused by data movement between analog computing elements and memory. Optoelectronic computing offers a promising alternative to traditional analog computing by bypassing the energy-bandwidth tradeoff and reducing latency. In analog computing architectures, analog-to-digital converters (ADCs) are essential for quantizing column-parallel computing results. However, ADCs with fixed resolution can result in unnecessary power consumption during low-resolution requirements. In this paper, we propose a hybrid ADC with a configurable resolution from 2 to 8-bit. The ADC integrates successive approximation register (SAR) and single-slope (SS) circuits to minimize the area and power consumption. The proposed ADC architecture was fabricated in 65nm CMOS process with a 1 V power supply. The prototype occupies an area of 177μm × 11μm and consumes 238μW in the 8-bit conversion mode. Measured results show that the ADC achieves an effective number of bits (ENOB) of 7.35 and a Walden figure of merit (FoMw)of 14.6 fJ/conv.

This paper proposes a novel hybrid-triggered electrostatic discharge (ESD) power clamp circuit. By co- optimizing the transient and static triggered paths, the proposed circuit can achieve transient response time over 6 times longer than that of traditional transient circuit in the same footprint, thus greatly improving area efficiency. The trigger circuit (TC) area of the proposed circuit reduces 50% compared to the baseline circuit. In addition, the circuit achieves high false- trigger immunity and low leakage current of 7 nA. The proposed circuit achieves adjustable transient response time to accommodate different ESD events with high flexibility. All the studied circuits are fabricated using a 28-nm CMOS process. To verify the proposed circuit, the simulation and test results are analyzed in detail for this paper.

This paper investigates the bigFET gate bias voltage in power-rail electrostatic discharge (ESD) clamp circuit for enhanced transient noise immunity. Based on a timed shutoff circuit, a resistor pair is employed to bias the bigFET gate voltage to different ratios of VDD. Through detailed investigations, an optimized bigFET gate bias scheme is proposed. With the optimized scheme, enhanced transient noise immunity of the investigated circuit is achieved. Besides, the optimized scheme can induce the channel and parasitic bipolar junction transistor parallel shunt paths in ESD events, which result in a lower on-resistance. Moreover, the optimized scheme is also validated in the high-threshold-voltage bigFET samples.

A power-rail electrostatic discharge clamp circuit with transient and static hybrid-detection enhanced triggering is proposed in this work. By skillfully co-optimizing the driving paths of both transient and static detection networks, the proposed circuit achieves a clamp device transient response time over 2 times longer than its RC time constant, which endows the proposed circuit with both promoted area-efficiency and safe clamping behaviors. Besides, the proposed circuit effectively combines the advantages of transient and static ones with tiny leakage current penalties. All investigated circuits are fabricated in a 65-nm CMOS process using 1.2-V thin-oxide devices. Simulation and test results are discussed in detail in this work to validate the proposed circuit.