Demo Data from SIGIR 2026 / reviewers in the wild / expert
Denis B. Jarvis
dblp:181/5134
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1963
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 67% Integrated circuit design · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › signal integrity
crosstalk mitigation |
0.0 | 1 | 1963 | The Effects of Interconnections on High-Speed Logic Circuits · IEEE Trans. Electron. Comput. 1963 |
Integrated circuit design › digital circuit design
high-speed digital circuits |
0.0 | 1 | 1963 | The Effects of Interconnections on High-Speed Logic Circuits · IEEE Trans. Electron. Comput. 1963 |
Electronic design automation
signal integrity |
0.0 | 1 | 1963 | The Effects of Interconnections on High-Speed Logic Circuits · IEEE Trans. Electron. Comput. 1963 |
Methods — techniques the papers use, named apart from their topics
worked examples · 0.0circuit speed analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1963 | The Effects of Interconnections on High-Speed Logic CircuitsabstractBy way of worked examples in typical but somewhat idealized cases the effect on circuit speed of circuit interconnections is studied. The source, calculation and minimization of interconnection crosstalk is also discussed. It is shown that high-speed circuitry must be miniaturized and the implications are discussed. Denis B. Jarvis |
IEEE Trans. Electron. Comput. | 1 |