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Warren A. Christopherson

dblp:182/0084 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1961
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 67% Integrated circuit design · 33%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › magnetic core memory
coincident-current memory
0.011961
Matrix Switch and Drive System for a Low-Cost Magnetic-Core Memory · IRE Trans. Electron. Comput. 1961
Memory systems
magnetic core memory
0.011961
Matrix Switch and Drive System for a Low-Cost Magnetic-Core Memory · IRE Trans. Electron. Comput. 1961
YearPublicationVenuePosition
1961 Matrix Switch and Drive System for a Low-Cost Magnetic-Core Memory
abstract
A unique system of ferrite-core matrix switches and drivers has been developed for a low-cost magnetic-core memory. The memory uses coincident-current techniques and has a capacity of 10,000 characters with seven bits per character. A 20-μsec read-compute-write cycle features serial-by-character processing. Approximately 7 μsec is computing time, and 13 μsec is read-write time. The matrix switch requires only two sets of five drivers to select one out of 100 individual outputs. The drivers operate in an unusual three-out-of-five coding arrangement. A Set and Reset a driver, each using four transistors in parallel, are also required for the matrix switch. Two matrix switches provide the 200 X-Y half-select drives for a 100 × 100 seven-plane core array. At read time, two half-select current pulses of 250 ma to 300 ma are emitted with an effective 10 per cent to 90 per cent rise time of 0.3 μsec. At write time, half-select current pulses with 1.2-μsec rise time are emitted on the same selected lines, but in the opposite direction. A new method of timing the drive current allows the read pulse to rise in 0.3 μsec, even with a low-voltage power supply and an inductive load that would otherwise limit the rise time to 0.8 μsec. All current-driving circuits use alloy junction transistors. The drive current is furnished from a 10 to 12 volt power supply, and temperature compensation of the drive currents is accomplished through control of power-supply voltage. Operating temperatures range from 10°C to 40°C.
Warren A. Christopherson
IRE Trans. Electron. Comput.1