A basic technique is presented which enables the development of Esaki diode NOT-OR logic circuits. Two embodiments of the basic scheme are discussed, which, when combined with an OR-DELAY circuit, provide a logically complete system. Emphasis is placed on the more economical of the two embodiments. A tolerance analysis is included, which demonstrates that the technique enables the practical design of logic circuits. The requirements placed on Esaki diode characteristics, and the speed limitations of the circuits, are discussed. Examples of working circuits are shown, including photographs of voltage wave shapes.