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Jiacheng Ma 0002

dblp:182/6469-2 · DBLP profile ↗
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5ranked-venue papers
3as first author
5since 2021 · last 2025
0009-0006-6907-7489ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 3 · 2 first-author · 3 since 2021Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Performance modeling and evaluation · 58% Hardware accelerators and domain-specific architectures · 24% Parallel and multicore computing · 15%
Software engineering, system software, and programming languages
2 papers
Runtime systems and virtual machines · 70% Operating systems · 30%

Topics — the 4 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation
simulation
0.912025
Fast End-to-End Performance Simulation of Accelerated Hardware-Software Stacks · SOSP 2025
Runtime systems and virtual machines
binary translation
0.612022
FPVM: Towards a Floating Point Virtual Machine · HPDC 2022
Parallel and multicore computing
parallel programming models
0.512021
Paths to OpenMP in the kernel · SC 2021
Parallel and multicore computing
parallel programming runtimes
0.112021
Paths to OpenMP in the kernel · SC 2021

Methods — techniques the papers use, named apart from their topics

trap-and-emulate · 1.1binary transformation · 1.1IR transformation · 1.1runtime porting · 1.0custom compilation · 1.0performance simulation · 0.9performance interfaces · 0.8
YearPublicationVenuePosition
2025 Fast End-to-End Performance Simulation of Accelerated Hardware-Software Stacks
Jiacheng Ma 0002, Jonas Kaufmann, Emilien Guandalino, Rishabh Iyer 0002, Thomas Bourgeat, George Candea
SOSP1
2024 Performance Interfaces for Hardware Accelerators
Jiacheng Ma 0002, Rishabh Iyer 0002, Sahand Kashani, Mahyar Emami, Thomas Bourgeat, George Candea
OSDI1
2023 The Case for Performance Interfaces for Hardware Accelerators
abstract
While systems designers are increasingly turning to hardware accelerators for performance gains, realizing these gains is painstaking and error-prone. It can take several person-months to determine if a given accelerator is a good fit for a given piece of code, and accelerators that cost millions of dollars to build can slow down the very systems they were designed to accelerate.
Rishabh Iyer 0002, Jiacheng Ma 0002, Katerina J. Argyraki, George Candea, Sylvia Ratnasamy
HotOS2
2022 FPVM: Towards a Floating Point Virtual Machine
abstract
Alternatives to IEEE floating point arithmetic have become all the rage. Some extract more representational power out of the available bits. Others offer the potential for lower or higher precision than is available in IEEE-compatible hardware. Even an "interface to the real numbers" has recently been proposed. Using such alternative arithmetic systems within an existing scientific or other significant codebase is a major challenge, however. We explore how to address this challenge through virtualizing the IEEE floating point hardware, specifically on x64. The goal of the floating point virtual machine (FPVM) is to allow an existing application binary to be seamlessly extended to support the desired alternative arithmetic system with overheads determined by that system and not the virtualization mechanisms. We describe the prospects, issues, and tradeoffs for four different approaches for building FPVM: trap-and-emulate, trap-and-patch, binary transformation, and IR transformation. We then describe the design and implementation of our current design, which combines static binary analysis/translation and trap-and-emulate execution. We evaluate our FPVM implementation on several benchmarks, virtualizing them to use posits and MPFR. Finally, we comment on kernel- and hardware-level innovations that could further reduce overheads for floating point virtualization.
Peter A. Dinda, Nick Wanninger, Jiacheng Ma 0002, Alex Bernat, Charles Bernat, Souradip Ghosh, Christopher Kraemer, Yehya Elmasry
HPDC3
2021 Paths to OpenMP in the kernel
abstract
OpenMP implementations make increasing demands on the kernel. We take the next step and consider bringing OpenMP into the kernel. Our vision is that the entire OpenMP application, run-time system, and a kernel framework is interwoven to become the kernel, allowing the OpenMP implementation to take full advantage of the hardware in a custom manner. We compare and contrast three approaches to achieving this goal. The first, runtime in kernel (RTK), ports the OpenMP runtime to the kernel, allowing any kernel code to use OpenMP pragmas. The second, process in kernel (PIK) adds a specialized process abstraction for running user-level OpenMP code within the kernel. The third, custom compilation for kernel (CCK), compiles OpenMP into a form that leverages the kernel framework without any intermediaries. We describe the design and implementation of these approaches, and evaluate them using NAS and other benchmarks.
Jiacheng Ma 0002, Aaron Nelson, Michael Cuevas, Brian Homerding, Conghao Liu, Simone Campanoni, Kyle C. Hale, Peter A. Dinda
SC1