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Joseph J. Karew

dblp:182/9795 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1960
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design
0.011960
System Application of Hybrid Logic Circuitry · IRE Trans. Electron. Comput. 1960
Integrated circuit design
digital system design
0.011960
System Application of Hybrid Logic Circuitry · IRE Trans. Electron. Comput. 1960
Integrated circuit design › digital circuit design
high-speed digital circuits
0.011960
System Application of Hybrid Logic Circuitry · IRE Trans. Electron. Comput. 1960

Methods — techniques the papers use, named apart from their topics

performance rating · 0.0bandwidth analysis · 0.0
YearPublicationVenuePosition
1960 System Application of Hybrid Logic Circuitry
abstract
A comparative performance rating of circuit techniques for performing logical functions in digital systems may be based upon: 1) Reliability and simplicity 2) Input and output capabilities 3) Propagation time 4) Cost. The ``Hybrid Transistor Diode Logic'' (HTDL) circuit technique employs either diodes or emitter follower transistors as gates and buffers, to maximize the circuit performance rating. The HTDL technique thus combines the advantages of lumped and distributed gain circuits. The cascading of diodes and emitter followers in logical gate matrices can be analyzed as the transmission of binary signals through a video system of a given bandwidth. The HTDL technique optimizes the use of the transistor through nonsaturating, low-impedance circuitry. This optimum use of 200-500 megacycle gain-bandwidth transistors is primarily limited by present-day packaging techniques and their inductive and capacitive loading effects upon the circuits. The development of macromodule packaging techniques, using 200-500 mc transistors, in HTDL circuitry, would permit system speeds (synchronous clock rates) to exceed 50 Mc.
John T. Lynch, Joseph J. Karew
IRE Trans. Electron. Comput.2