Demo Data from SIGIR 2026 / reviewers in the wild / expert
Fabricio Ferracioli
dblp:184/0751
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 56% Electronic design automation · 44% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization › accelerator compilation
heterogeneous compilation |
0.3 | 1 | 2017 | Static placement of computation on heterogeneous devices · Proc. ACM Program. Lang. 2017 |
Parallel and multicore computing › parallel algorithms › parallel algorithm design
parallel algorithm mapping |
0.3 | 1 | 2017 | Static placement of computation on heterogeneous devices · Proc. ACM Program. Lang. 2017 |
Electronic design automation › hardware verification and test
static analysis |
0.3 | 1 | 2017 | Static placement of computation on heterogeneous devices · Proc. ACM Program. Lang. 2017 |
Parallel and multicore computing
parallel programming models |
0.1 | 1 | 2017 | Static placement of computation on heterogeneous devices · Proc. ACM Program. Lang. 2017 |
Methods — techniques the papers use, named apart from their topics
simulated annealing · 0.6cost model · 0.6call graph analysis · 0.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | Static placement of computation on heterogeneous devicesabstractHeterogeneous architectures characterize today hardware ranging from super-computers to smartphones. However, in spite of this importance, programming such systems is still challenging. In particular, it is challenging to map computations to the different processors of a heterogeneous device. In this paper, we provide a static analysis that mitigates this problem. Our contributions are two-fold: first, we provide a semi-context-sensitive algorithm, which analyzes the program's call graph to determine the best processor for each calling context. This algorithm is parameterized by a cost model, which takes into consideration processor's characteristics and data transfer time. Second, we show how to use simulated annealing to calibrate this cost model for a given heterogeneous architecture. We have used our ideas to build Etino, a tool that annotates C programs with OpenACC or OpenMP 4.0 directives. Etino generates code for a CPU-GPU architecture without user intervention. Experiments on classic benchmarks reveal speedups of up to 75x. Moreover, our calibration process lets avoid slowdowns of up to 720x which trivial parallelization approaches would yield. Gabriel Poesia, Breno Campos Ferreira Guimarães, Fabricio Ferracioli, Fernando Magno Quintão Pereira |
Proc. ACM Program. Lang. | 3 |
| 2016 | ParallelME: A Parallel Mobile Engine to Explore Heterogeneity in Mobile Computing Architectures
Guilherme Andrade, Wilson de Carvalho, Renato Utsch, Pedro Caldeira, Alberto Albuquerque, Fabricio Ferracioli, Leonardo Rocha 0001, Michael Frank 0008, Dorgival O. Guedes, Renato Ferreira 0001 |
Euro-Par | 6 |