Demo Data from SIGIR 2026 / reviewers in the wild / expert
Stephen Mallon
dblp:185/1063
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 2019
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorComputer networks · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Interconnection networks and networks-on-chip · 61% Performance modeling and evaluation · 21% Parallel and multicore computing · 18% | |
| Computer networks
1 paper |
Network measurement and analytics · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 100% | |
| Network and information security
1 paper |
Systems and software security · 100% |
Topics — the 4 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Network measurement and analytics
latency measurement |
0.4 | 1 | 2019 | Lancet: A self-correcting Latency Measuring Tool · USENIX ATC 2019 |
Operating systems › operating system design
library operating systems |
0.3 | 1 | 2018 | DLibOS: Performance and Protection with a Network-on-Chip · ASPLOS 2018 |
Interconnection networks and networks-on-chip › interprocessor communication
hardware message passing |
0.3 | 1 | 2018 | DLibOS: Performance and Protection with a Network-on-Chip · ASPLOS 2018 |
Parallel and multicore computing
many-core systems |
0.1 | 1 | 2018 | DLibOS: Performance and Protection with a Network-on-Chip · ASPLOS 2018 |
Methods — techniques the papers use, named apart from their topics
network-on-chip · 1.0hardware message passing · 1.0asynchronous socket interface · 1.0self-correction · 0.8latency measurement · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2019 | Lancet: A self-correcting Latency Measuring Tool
Marios Kogias, Stephen Mallon, Edouard Bugnion |
USENIX ATC | 2 |
| 2018 | DLibOS: Performance and Protection with a Network-on-ChipabstractA long body of research work has led to the conjecture that highly efficient IO processing at user-level would necessarily violate protection. In this paper, we debunk this myth by introducing DLibOS a new paradigm that consists of distributing a library OS on specialized cores to achieve performance and protection at the user-level. Its main novelty consists of leveraging network-on-chip to allow hardware message passing, rather than context switches, for communication between different address spaces. To demonstrate the feasibility of our approach, we implement a driver and a network stack at user-level on a Tilera many-core machine. We define a novel asynchronous socket interface and partition the memory such that the reception, the transmission and the application modify isolated regions. Our high performance results of 4.2 and 3.1 million requests per second obtained on a webserver and the Memcached applications, respectively, confirms the relevance of our design decisions. Finally, we compare DLibOS against a non-protected user-level network stack and show that protection comes at a negligible cost. Stephen Mallon, Vincent Gramoli, Guillaume Jourjon |
ASPLOS | 1 |
| 2016 | Are Today's SDN Controllers Ready for Primetime?abstractSDN efficiency is driven by the ability of controllers to process small packets based on a global view of the network. The goal of such controllers is thus to treat new flows coming from hundreds of switches in a timely fashion. In this paper, we show this ideal remains impossible through the most extensive evaluation of SDN controllers. We evaluated five state-of-the-art SDN controllers and discovered that the most efficient one spends a fifth of his time in packet serialization. More dramatically, we show that this limitation is inherent to the object oriented design principle of these controllers. They all treat each single packet as an individual object, a limitation that induces an unaffordable per-packet overhead. To eliminate the responsibility of the hardware from our results, we ported these controllers on a network-efficient architecture, Tilera, and showed even worse performance. We thus argue for an in-depth rethinking of the design of the SDN controller into a lower level software that leverages both operating system optimizations and modern hardware features. Stephen Mallon, Vincent Gramoli, Guillaume Jourjon |
LCN | 1 |