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Prasanna Kansakar

dblp:185/5760 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2018
0000-0002-5454-1772ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Performance modeling and evaluation · 46% Processor architecture and microarchitecture · 30% Electronic design automation · 23%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
chip multiprocessor
0.312018
A Design Space Exploration Methodology for Parameter Optimization in Multicore Processors · IEEE Trans. Parallel Distributed Syst. 2018
Performance modeling and evaluation › simulation › architectural simulation
cycle-accurate simulation
0.312018
A Design Space Exploration Methodology for Parameter Optimization in Multicore Processors · IEEE Trans. Parallel Distributed Syst. 2018
Electronic design automation
design space exploration
0.312018
A Design Space Exploration Methodology for Parameter Optimization in Multicore Processors · IEEE Trans. Parallel Distributed Syst. 2018
Performance modeling and evaluation
simulation
0.312018
A Design Space Exploration Methodology for Parameter Optimization in Multicore Processors · IEEE Trans. Parallel Distributed Syst. 2018

Methods — techniques the papers use, named apart from their topics

exhaustive search · 0.3design space exploration · 0.3
YearPublicationVenuePosition
2018 A Design Space Exploration Methodology for Parameter Optimization in Multicore Processors
abstract
The need for application-specific design of multicore/manycore processing platforms is evident with computing systems finding use in diverse application domains. In order to tailor multicore/manycore processors for application specific requirements, a multitude of processor design parameters have to be tuned accordingly which involves rigorous and extensive design space exploration over large search spaces. In this paper, we propose an efficient methodology for design space exploration. We evaluate our methodology over two search spaces small and large, using a cycle-accurate simulator (ESESC) and a standard set of PARSEC and SPLASH-2 benchmarks. For the smaller design space, we compare results obtained from our design space exploration methodology with results obtained from fully exhaustive search. The results show that solution quality obtained from our methodology are within 1.35 - 3.69 percent of the results obtained from fully exhaustive search while only exploring 2.74 - 3 percent of the design space. For larger design space, we compare solution quality of different results obtained by varying the number of tunable processor design parameters included in the exhaustive search phase of our methodology. The results show that including more number of tunable parameters in the exhaustive search phase of our methodology greatly improves solution quality.
Prasanna Kansakar, Arslan Munir
IEEE Trans. Parallel Distributed Syst.1