This article presents a layout-aware area optimization methodology for transposable spin-transfer torque magnetic random access memory (STT-MRAM). Although transposable STT-MRAM achieves high performance in processing-in-memory (PIM) systems for a spiking neural network (SNN), challenges in layout design and optimization remain owing to the vertical arrangement of its two wordlines (WLs). We propose three different layout design techniques to address these challenges. We also analyze the cell area changes of our proposed layout design according to the width of two access transistors. The proposed layout designs for transposable STT-MRAM are implemented in a 28-nm CMOS technology coupled with a SPICE-compatible model for a magnetic tunnel junction. Results show that in the metal pitch limited region, our proposed perpendicular poly with metal column-WL-based layout design achieves minimum cell area, with at least 5.3% area savings in comparison with other proposed layout designs. Furthermore, by targeting an identical design specification of 35% write margin (WM) and 160% cell tunnel magnetoresistance, the resulting cell area falls in the transistor width-limited region. In this case, our proposed parallel poly with metal-WL-based layout design achieves at least 21% area savings compared with the other proposed layout designs. This result demonstrates that our proposed layout design and analysis offer valuable insights for circuit designers in selecting the optimal design that meets target specifications and requirements.

Emerging device based spiking neural network (SNN) hardware design has been actively studied. Especially, energy and area efficient synapse crossbar has been of particular interest, but processing units for weight summations in synapse crossbar are still a main bottleneck for energy and area efficient hardware design. In this paper, we propose an efficient SNN architecture with stochastic spin-orbit torque (SOT) device based multi-bit synapses. First, we present SOT device based synapse array using modified gray code. The modified gray code based synapse needs only N devices to represent 2^N levels of synapse weights. Accumulative spike technique is also adopted in the proposed synapse array, to improve ADC utilization and reduce the number of neuron updates. In addition, we propose hardware friendly algorithmic techniques to improve classification accuracies as well as energy efficiencies. Non-spike depression based stochastic spike-timing-dependent plasticity is used to reduce the overlapping input representation and classification error. Early read termination is also employed to reduce energy consumption by turning off less associated neurons. The proposed SNN processor has been implemented using 65nm CMOS process, and it shows 90% classification accuracy in MNIST dataset consuming 0.78J/image (training) and 0.23J/image (inference) of energy with an area of 1.12mm2.

Although considered as one of the most viable emerging non-volatile memory, the spin-transfer-torque magnetic random access memory (STT-MRAM) suffers from its weakness in the write operation. Spin-orbit torque magnetic random access memory (SOT-MRAM) has been recently proposed to provide lower write energy consumption. Nevertheless, additional write energy reduction is still on demand for embedded memory purposes. In this paper, we propose an early write termination (EWT) technique for SOT-MRAM, which can greatly reduce the write energy consumption by efficiently removing the unnecessarily long write pulse. The proposed Dynamic Reference Early Termination (DRET) scheme provides energy savings in all write operations while guaranteeing reliable operation. Simulation results using 65nm CMOS technology show that 76.6% of write energy can be saved on average compared to the conventional SOT-MRAM.

Nonvolatile flip-flop (NVFF) using spin-transfer torque magnetic tunnel junctions (STT-MTJs) has been proposed to enable line-grain power gating systems. However, the STT-MTJ-based NVFF (STT-NVFF) may not perform fast backup and disturb-free restore operations. We propose a new NVFF using complementary polarizer MTJ (CPMTJ) to alleviate these limitations. Our proposed NVFF exploits the CPMTJ structure for fast- and low-energy backup operation. The estimated backup delay is less than 10 ns in 7-nm node FinFET technology with CPMTJ size of 12 nm × 33 nm in a rectangular shape. Furthermore, during the restore operation, CPMTJ provides guaranteed disturb-free sensing, since the disturb torque from the two complementary pinned layers of CPMTJ cancels each other. The simulation results show 2 times improvement in the backup delay with higher restore-disturb margin compared with STT-NVFF.