Demo Data from SIGIR 2026 / reviewers in the wild / expert
Chao Wang 0051
dblp:188/7759-51
· DBLP profile ↗
4ranked-venue papers
1as first author
1since 2021 · last 2023
0000-0002-1083-109XORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Memory systems · 42% Parallel and multicore computing · 42% Hardware accelerators and domain-specific architectures · 12% | |
| Databases, data mining, and information retrieval
1 paper |
Graph data management · 100% | |
| Artificial intelligence
1 paper |
Efficient and distributed learning · 100% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing
graph processing |
0.7 | 2 | 2019 | GraphQ: Scalable PIM-Based Graph Processing · MICRO 2019 GraphP: Reducing Communication for PIM-Based Graph Processing with Efficient Data Partition · HPCA 2018 |
Memory systems
processing-in-memory |
0.7 | 2 | 2019 | GraphQ: Scalable PIM-Based Graph Processing · MICRO 2019 GraphP: Reducing Communication for PIM-Based Graph Processing with Efficient Data Partition · HPCA 2018 |
Graph data management › graph processing
graph processing systems |
0.4 | 1 | 2019 | GraphQ: Scalable PIM-Based Graph Processing · MICRO 2019 |
Parallel and multicore computing
data distribution |
0.3 | 1 | 2018 | GraphP: Reducing Communication for PIM-Based Graph Processing with Efficient Data Partition · HPCA 2018 |
Memory systems › processing-in-memory
PIM-based graph processing |
0.3 | 1 | 2018 | GraphP: Reducing Communication for PIM-Based Graph Processing with Efficient Data Partition · HPCA 2018 |
Machine learning › Efficient and distributed learning
model compression |
0.3 | 1 | 2017 | CirCNN: accelerating and compressing deep neural networks using block-circulant weight matrices · MICRO 2017 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.3 | 1 | 2017 | CirCNN: accelerating and compressing deep neural networks using block-circulant weight matrices · MICRO 2017 |
Methods — techniques the papers use, named apart from their topics
irregular data movement optimization · 0.8block-circulant matrix multiplication · 0.6hybrid memory cubes · 0.4hybrid memory cube · 0.4two-phase vertex program · 0.3source-cut partitioning · 0.3hierarchical communication · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | RDMA-Enabled Concurrency Control Protocols for Transactions in the Cloud EraabstractOnline transaction processing (OLTP) is widely used on modern cloud infrastructures to complete important businesses such as payments and stock exchanges. Remote Direct Memory Access (RDMA) is a technology that enables ultra-low inter-server memory access latency - which is critical for implementing high-performance concurrency control protocols in distributed OLTP. In this article, we develop RCC, the first unified and comprehensive RDMA-enabled distributed transaction processing framework containing six serializable concurrency control protocols—not only the classical protocols${{\sf NOWAIT}}$,${{\sf WAITDIE}}$,${{\sf OCC}}$, but also more advanced${{\sf MVCC}}$,${{\sf SUNDIAL}}$, and${{\sf CALVIN}}$— the deterministic protocol. Our goal is to unbiasedly compare protocols on OLTP workloads in a common execution environment with the concurrency control protocol being the only changeable component. From RCC, we obtained new insights on building RDMA-based protocols. We analyzed stage-wise latency breakdown to develop more efficient hybrid implementations. Moreover, RCC can enumerate all stage-wise hybrid designs under a given workload characteristic. Our results show that throughput-wise hybrid designs are better than RPC or one-sided counterparts by 32.2% and up to 67%; three hybrid designs are better than their pure counterparts by up to 17.8%. RCC can provide performance insights and be used as the common open-sourced infrastructure for fast prototyping new implementations. Chao Wang 0051, Xuehai Qian |
IEEE Trans. Cloud Comput. | 1 |
| 2019 | GraphQ: Scalable PIM-Based Graph ProcessingabstractProcessing-In-Memory (PIM) architectures based on recent technology advances (e.g., Hybrid Memory Cube) demonstrate great potential for graph processing. However, existing solutions did not address the key challenge of graph processing---irregular data movements. Youwei Zhuo, Chao Wang 0051, Rui Wang 0014, Dimin Niu, Yanzhi Wang 0001, Xuehai Qian |
MICRO | 2 |
| 2018 | GraphP: Reducing Communication for PIM-Based Graph Processing with Efficient Data PartitionabstractProcessing-In-Memory (PIM) is an effective technique that reduces data movements by integrating processing units within memory. The recent advance of “big data” and 3D stacking technology make PIM a practical and viable solution for the modern data processing workloads. It is exemplified by the recent research interests on PIM-based acceleration. Among them, TESSERACT is a PIM-enabled parallel graph processing architecture based on Micron's Hybrid Memory Cube (HMC), one of the most prominent 3D-stacked memory technologies. It implements a Pregel-like vertex-centric programming model, so that users could develop programs in the familiar interface while taking advantage of PIM. Despite the orders of magnitude speedup compared to DRAM-based systems, TESSERACT generates excessive crosscube communications through SerDes links, whose bandwidth is much less than the aggregated local bandwidth of HMCs. Our investigation indicates that this is because of the restricted data organization required by the vertex programming model. In this paper, we argue that a PIM-based graph processing system should take data organization as a first-order design consideration. Following this principle, we propose GraphP, a novel HMC-based software/hardware co-designed graph processing system that drastically reduces communication and energy consumption compared to TESSERACT. GraphP features three key techniques. 1) “Source-cut” partitioning, which fundamentally changes the cross-cube communication from one remote put per cross-cube edge to one update per replica. 2) “Two-phase Vertex Program”, a programming model designed for the “source-cut” partitioning with two operations: GenUpdate and ApplyUpdate. 3) Hierarchical communication and overlapping, which further improves performance with unique opportunities offered by the proposed partitioning and programming model. We evaluate GraphP using a cycle accurate simulator with 5 real-world graphs and 4 algorithms. The results show that it provides on average 1.7 speedup and 89% energy saving compared to TESSERACT. Youwei Zhuo, Chao Wang 0051, Mingyu Gao 0001, Yongwei Wu 0001, Kang Chen 0001, Christoforos E. Kozyrakis, Xuehai Qian |
HPCA | 3 |
| 2017 | CirCNN: accelerating and compressing deep neural networks using block-circulant weight matricesabstractLarge-scale deep neural networks (DNNs) are both compute and memory intensive. As the size of DNNs continues to grow, it is critical to improve the energy efficiency and performance while maintaining accuracy. For DNNs, the model size is an important factor affecting performance, scalability and energy efficiency. Weight pruning achieves good compression ratios but suffers from three drawbacks: 1) the irregular network structure after pruning, which affects performance and throughput; 2) the increased training complexity; and 3) the lack of rigirous guarantee of compression ratio and inference accuracy. Caiwen Ding, Siyu Liao, Yanzhi Wang 0001, Zhe Li 0001, Ning Liu 0007, Youwei Zhuo, Chao Wang 0051, Xuehai Qian, Yu Bai 0004, Geng Yuan, Jian Tang 0008, Qinru Qiu, Xue Lin 0001, Bo Yuan 0001 |
MICRO | 7 |