Conventionally, glitch reduction is well-studied in digital design to improve power, efficiency, and security. In contrast, this paper combines the addition and removal of glitches to minimize the power side-channel leakage. Glitch Manipulation is achieved through gate sizing-based arrival time control, which is cast as a Geometric Programming formulation. We develop a framework, GLiTCH, for glitch manipulation that is guided by functional and timing simulations. The framework is evaluated on popular cipher designs like AES, CLEFIA, and SM4. Our findings illustrate up to 52.82% improvement in the Guessing Entropy for a 38.74% area overhead on average across the evaluated ciphers.

The problem of gate sizing to meet timing specification while minimizing functional power/area is well understood and is solved by the use of geometric programs (GPs). While these area minimization GP (AM-GP) formulations minimize functional power, they do not address the problem of glitches. Glitches are extraneous transitions caused by signal arrival time imbalance at the input nodes of logic gates. A gate sizing algorithm, area-glitch minimization GP (AGM-GP), is proposed to reduce glitches while constraining area and adhering to a timing specification. Glitch reduction is achieved through signal arrival time balancing posed as posynomials in a GP formulation. Prior art does not exploit the complete power of gate sizing when reducing glitches in an attempt to meet the timing specification. In particular, the proposed formulation allows both upsizing and downsizing without causing any timing violation, at the expense of a marginal increase in area. Traditional downsizing methods can be used to further reduce glitches over and above the AGM-GP solution. Simulation results on the ISCAS-85 benchmark circuits show an overall reduction of 20.4% glitch power and 9.5% total power which is, respectively, 13.8% and 3.9% better than just downsizing the AM-GP solution. This power reduction was achieved with an average area increase of 4.2%.

Area and energy-efficient data converters are an integral part of In-Memory Compute (IMC) engines. The conventional Digital to Analog Converters (DACs) uses binary-weighted pull-up current sources with scan-flops feeding in the digital input. These bulky pull-up devices and scan-flops make it hard to integrate along-side a memory array in an area-efficient manner. Further, it is prone to error due to local variations owing to limited digital control. In this paper, we propose an area-efficient, Word-Line (WL) pitch-aligned, layout friendly In-Memory compatible DAC (IM-DAC), whose layout resembles the 8T SRAM array very closely, thus achieving memory array-like density. Simulation results show that the worst-case INL and DNL is 2.42 LSB and -0.32 LSB, respectively. We obtained a 3.4X area advantage in comparison with the conventional DAC. The high-density layout allows for additional calibration pull-up stacks, with minimal area penalty, that reduces the standard deviation of the linearized-current to 48.76% of the corresponding value before calibration.

In memory computing is gaining traction as a technique to implement the Multiply Accumulate (MAC) operation on edge network devices, to perform neural network inference while reducing energy expended in memory-fetch. The voltage developed along a bit-line is an analog representation of the MAC value and needs to be digitized for further processing. In this paper we propose to use the Sense Amp as a comparator to perform the digitization using a serial flash, implemented in memory. Flash ADCs require an ordered set of reference voltages to compare against the input to be digitized. Recognizing that the MAC value is non-uniformly distributed and is application specific we propose an algorithm to generate the reference voltages tailored to the MAC distribution function. Further, we show that the reference voltage can be generated in much the same way as the MAC voltage is generated along a column, in-memory. We provide an algorithm to populate the bit-cells of the reference column to generate the appropriate reference voltage. Experiments on the MNIST, SVHN and CIFAR-10 data sets show that the proposed technique results in a worst case accuracy reduction of 0.8% compared to the Double-Precision evaluation.

A technique for extracting statistical compact model parameters using artificial neural networks (ANNs) is proposed. ANNs can model a much higher degree of nonlinearity compared to existing quadratic polynomial models and, hence, can even be used in sub-100-nm technologies to model leakage current that exponentially depends on process parameters. Existing techniques cannot be extended to handle such exponential functions. Additionally, ANNs can handle multiple input multiple output relations very effectively. The concept applied to CMOS devices improves the efficiency and accuracy of model extraction. Results from the ANN match the ones obtained from SPICE simulators within 1%.

Artificial neural networks (ANNs) have shown great promise in modeling circuit parameters for computer aided design applications. Leakage currents, which depend on process parameters, supply voltage and temperature can be modeled accurately with ANNs. However, the complex nature of the ANN model, with the standard sigmoidal activation functions, does not allow analytical expressions for its mean and variance. We propose the use of a new activation function that allows us to derive an analytical expression for the mean and a semi-analytical expression for the variance of the ANN-based leakage model. To the best of our knowledge this is the first result in this direction. Our neural network model also includes the voltage and temperature as input parameters, thereby enabling voltage and temperature aware statistical leakage analysis (SLA). All existing SLA frameworks are closely tied to the exponential polynomial leakage model and hence fail to work with sophisticated ANN models. In this paper, we also set up an SLA framework that can efficiently work with these ANN models. Results show that the cumulative distribution function of leakage current of ISCAS'85 circuits can be predicted accurately with the error in mean and standard deviation, compared to Monte Carlo-based simulations, being less than 1% and 2% respectively across a range of voltage and temperature values.