A new VLSI CAD environment considering stochastic behavior of MTJ devices is proposed for the evaluation of not only the performance but also the reliability of MTJ/MOS-hybrid logic LSI. The proposed simulator allows users to support the design of MTJ/MOS-hybrid LSI by RTL/gate-level hardware description, whose simulation considering stochastic switching behavior of MTJ device can be done by analog-mixed-signal simulation with de-facto standard EDA tools. Through the design of a nonvolatile logic LSI based on a general purpose 32-bit microprocessor, the impact of the proposed design flow is demonstrated.

Nonvolatile spintronic devices have potential advantages, such as fast read/write and high endurance together with back-end-of-the-line compatibility, which offers the possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also standby-power-free high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages of employing spintronic devices, especially magnetic tunnel junction (MTJ) devices with CMOS circuits, are discussed, and the current status of the MTJ-based VLSI computing paradigm is presented along with its prospects and remaining challenges.

Provides an overview of the technical articles and features presented in this issue.

Recent advances in spintronics devices make it possible to open a new era of microelectronics. In this paper, we review the spintronics devices utilizing spin-transfer torques (STTs) and spin-orbit torques (SOTs) developed in recent years. The progresses of two-terminal STT device with CoFeB-MgO based magnetic tunnel junction (MTJ), three-terminal magnetic domain wall (DW) motion device with Co/Ni multilayer, and three-terminal SOT device with Cu-based channel are described. Integrated circuits with the developed spintronics devices are also reviewed.

A delay circuit using four-terminal magnetic-random-access-memory (MRAM) devices was designed for power-efficient time-domain signal processing. A cell area of 6.4 μm2was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit.

A perpendicular magnetic-tunnel-junction (MTJ)-based 2T-2R ternary content-addressable memory (TCAM) cell is proposed for a high-density nonvolatile word-parallel/bit-serial TCAM. The use of MOS/MTJ-hybrid logic makes it possible to implement a compact nonvolatile TCAM cell with 2.5 μm2of a cell size in a 0.14-μm CMOS and a 100-nm perpendicular-MTJ technologies. By reversed-current reading through the perpendicular MTJ device, tolerability of read disturb is greatly enhanced. Moreover, fine-grained power gating based on bit-level equality-search scheme achieves ultra-low activity rate of 4.1% in a fabricated 72-bit × 128-word nonvolatile TCAM, which results in ultra-low active power and standby power.

An extremely practical simulation program with integrated circuits emphasis (SPICE) incorporating model parameters of magnetic tunnel junction (MTJ) was developed. The simulator provides reliable simulation results in spintronics circuit design because it can accurately calculate various MTJ characteristics that actual devices have, that considerably influence the operation margin and power dissipation. It can also accelerate the simulation speed, which makes it possible to simulate three times or more large-scale circuits than when a conventional macro-model is used.

Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. This paper presents novel nonvolatile logic circuits based on logic-in-memory architecture using magnetic tunnel junctions (MTJs) in combination with MOS transistors. Since the MTJ with a spin-injection write capability is only one device that has all the following superior features as large resistance ratio, virtually unlimited endurance, fast read/write accessibility, scalability, complementary MOS (CMOS)-process compatibility, and nonvolatility, it is very suited to implement the MOS/MTJ-hybrid logic circuit with logic-in-memory architecture. A concrete nonvolatile logic-in-memory circuit is designed and fabricated using a 0.18 mum CMOS/MTJ process, and its future prospects and issues are discussed.

In this paper, we propose a novel image sensor which compresses image signals on the sensor plane. Since an image signal is compressed on the sensor plane by making use of the parallel nature of image signals, the amount of signal read out from the sensor can be significantly reduced. Thus, the potential applications of the proposed sensor are high pixel rate cameras and processing systems which require very high speed imaging or very high resolution imaging. The very high bandwidth is the fundamental limitation to the feasibility of those high pixel rate sensors and processing systems. Conditional replenishment is employed for the compression algorithm. In each pixel, current pixel value is compared to that in the last replenished frame. The value and the address of the pixel are extracted and coded if the magnitude of the difference is greater than a threshold. Analog circuits have been designed for processing in each pixel. A first prototype of a VLSI chip has been fabricated. Some results of experiments obtained by using the first prototype are shown in this paper.

A novel image sensor on which video signals can be compressed is proposed. Since the video signal is compressed on an imager plane by using fast analog processing, the amount of image data read out from the imager can be significantly reduced with very small latency. The proposed system can be potentially applied to high pixel rate cameras such as those for high speed imaging and high resolution imaging. Conditional replenishment is employed for the video compression algorithm. Analog circuits are designed both for processing in each pixel and for controlling the entire data rate. The behavior of the circuit is investigated on the basis of both an analog circuit simulator and a scale-up-circuit. A VLSI chip is designed and is under fabrication.>