Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from SIGIR 2026 / reviewers in the wild / expert

Takaaki Hagiwara

dblp:191/9283 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
0since 2021 · last 1985
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Electronic design automation · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › analog and mixed-signal circuits
device modeling		 0.011985
Three-Dimensional Device Simulator CADDETH with Highly Convergent Matrix Solution Algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1985
Electronic design automation › technology computer-aided design › device simulation
three-dimensional device simulation		 0.011985
Three-Dimensional Device Simulator CADDETH with Highly Convergent Matrix Solution Algorithms · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1985

Methods — techniques the papers use, named apart from their topics

vectorization · 0.0matrix solution algorithms · 0.0
YearPublicationVenuePosition
1985 Three-Dimensional Device Simulator CADDETH with Highly Convergent Matrix Solution Algorithms
abstract
A practical three-dimensional device simulator CADDETH (Computer Aided Device DEsign in THree dimensions) has been developed. Matrix solution methods appropriate to three-dimensional analyses have been devised. A vectorization ratio of 97 percent has been attained through efficient use of S-810 super computer with vectorized coding, resulting in a computation speed 16 times greater than can be obtained with S-810 in scalar mode computation. Full avalanche breakdown of MOSFET's can be readily simulated with good convergence and good agreement with experimental results.
Toru Toyabe, Hiroo Masuda, Yukio Aoki, Hiroko Shukuri, Takaaki Hagiwara
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5