Efficient architectures and implementations of median filters have been well investigated in the past. In this article, we focus on median filters for very big scientific applications with very large windows and an infinite stream of data, inspired by big data needs in the Square Kilometre Array (SKA) pulsar search engine, but transferable to other big data domains. We propose a novel approach for very large rectangular windows on an FPGA accelerator device able to support the processing of infinite streams of data. OpenCL is used for rapid parameter sweeping and design space exploration based on a pipelined model of the system. Evaluation on a host/accelerator system with an Arria 10 device surpassed 64 million values processed per second considered for the SKA real time requirement, achieving 83.4M value/s while reading from/writing to disk. These results are compared with a state-of-the-art software implementation only achieving 41M value/s for over twice the total system energy cost.

The Square Kilometre Array (SKA) project will be the world’s largest radio telescope array. With its large number of antennas, the number of signals that need to be processed is dramatic. One important element of the SKA’s Central Signal Processor package is pulsar search. This article focuses on the FPGA-based acceleration of the Frequency-Domain Acceleration Search module, which is a part of SKA pulsar search engine. In this module, the frequency-domain input signals have to be processed by 85 Finite Impulse response (FIR) filters within a short period of limitation and for thousands of input arrays. Because of the large scale of the input length and FIR filter size, even high-end FPGA devices cannot parallelise the task completely. We start by investigating both time-domain FIR filter (TDFIR) and frequency-domain FIR filter (FDFIR) to tackle this task. We applied the overlap-add algorithm to split the coefficient array of TDFIR and the overlap-save algorithm to split the input signals of FDFIR. To achieve fast prototyping design, we employed OpenCL, which is a high-level FPGA development technique. The performance and power consumption are evaluated using multiple FPGA devices simultaneously and compared with GPU results, which is achieved by porting FPGA-based OpenCL kernels. The experimental evaluation shows that the FDFIR solution is very competitive in terms of performance, with a clear energy consumption advantage over the GPU solution.

The Square Kilometer Array, which will be the world's largest radio telescope, will enhance and boost a large number of science projects, including the search for pulsars. The frequency-domain acceleration search is an efficient approach to search for binary pulsars. A significant part of it is the harmonic-summing module, which is the research subject of this paper. Most of the operations in the harmonic-summing module are relatively cheap operations for field-programmable gate arrays (FPGAs). The main challenge is the large number of point accesses to off-chip memory, which are not consecutive but irregular. Having the harmonic summing on the FPGA will avoid off-board communication with other pulsar search modules, which could destroy other acceleration benefits. Two types of harmonic-summing approaches are investigated in this paper: (1) storing intermediate data in off-chip memory and (2) processing the input signals directly without storing. For the second type, two approaches of caching data are proposed and evaluated: (1) preloading points that are frequently touched and (2) preloading all necessary points that are used to generate a chunk of output points. Open Computing Language (OpenCL) is adopted to implement the proposed approaches. In an extensive experimental evaluation, the same OpenCL kernel codes are evaluated on FPGA boards and GPU cards. Regarding the proposed preloading methods, preloading all necessary points method while reordering the input signals is faster than all the other methods. While in raw performance, a single-FPGA board cannot compete with a GPU. Regarding energy dissipation, GPU costs up to 2.6× times more energy than that of FPGAs in executing the same NDRange kernels.

Large scale median filtering algorithms are investigated in the context of the Square Kilometre Array (SKA) pulsar search; a signal processing pipeline estimated to require more than 10POps on 60PB of search data collected per day. Real time performance is needed for rectangular median windows of 63 frequency channels across 1023 time steps, requiring at least 64 million values to be calculated and output per second. This paper proposes an algorithmic approach for large scale median filtering based on existing techniques, providing improvements for the heterogeneous system used and utilising a high-end FPGA accelerator. Taking advantage of OpenCL for rapid parameter sweeping, the design space was explored to find the best algorithmic approach. The evaluation results are promising and show output of up to 99.3 million values per second on an Arria-10 FPGA, coming close to the limits set by resources and bandwidth. These results are set into relation with GPU and CPU implementations for the same algorithm, taking advantage of the OpenCL portability, achieving up to 16.8 and 9.1Mvalue/s respectively.

High-level approaches to hardware development can expedite the design process, allowing for rapid design space exploration. However, in order to generate optimised solutions expert intervention is often still required. This work seeks to explore the relationship between high-level descriptions and the resulting hardware architecture. This aims to reduce the barrier to entry for software developers (without hardware expertise) to produce optimised hardware designs through application of classical loop optimisation techniques. An algorithm from the Square Kilometre Array (SKA) is chosen to demonstrate the effects of such changes in a real world, real-time application requiring high throughput and low power consumption, taking a systematic approach in order to achieve an optimised result. A systolic array design is also discussed and compared with the software style changes. The Intel FPGA SDK for OpenCL (AOCL) Offline Compiler (AOC) is used here for verification and synthesis of the designs being examined, targeting an Arria-10 FPGA accelerator.

Pulsar search is one of the main tasks for the Square Kilometre Array (SKA) central signal processor (CSP) sub-element. Because most of the pulsar details are unknown, many pulsar search approaches are employed. The main compute-intensive application of the pulsar search modules is the matched filter group, which convolves the input signals with a group of filters. High-performance designs on FPGAs have been proposed that can process multiple large filters efficiently. But given that in many applications, including the here targeted pulsar search, filters have different sizes, there is a high potential for optimisation. This paper investigates the optimisation of general matched filtering design for the SKA pulsar search engine. The influence of changing the number of filters and the difference in sizes is analysed. The general implementations in time-domain (TD) and frequency-domain (FD) are optimised, employing the longest processing time (LPT) first rule to distribute filter templates across filter processing pipelines. The proposed design is employed to implement the matched filter groups in two SKA pulsar modules. The results show that the optimisation can provide up to 2.1× speedup in TD and 1.2× speedup in FD.

The Square Kilometre Array (SKA) project will be the world largest radio telescope array. With the growth of the number of antennas, the signals that need to be processed increase dramatically. One import element of the SKA central signal processor (CSP) package is pulsar search. This paper focuses on the FPGA-based acceleration of the frequency-domain acceleration search (FDAS) module, part of SKA pulsar search. In FDAS, the frequency-domain input signals have to be processed by 85 421-tap FIR filters within a short time limit and for thousands of input arrays. Because of the large scale of input length and FIR filter size, even high-end FPGA devices cannot parallelize the task completely. We start by investigating both time-domain FIR filter (TDFIR) and frequency-domain FIR filter (FDFIR) to tackle the FDAS task. We applied the overlap-add algorithm (OLA) to split the coefficient array of TDFIR and the overlap-save algorithm (OLS) to split the input signals of FDFIR. To achieve fast prototyping design, we applied OpenCL, which is a high-level FPGA development technique, to develop high-end FPGAs. The performance and power consumption are evaluated and compared with GPU results, which is achieved by porting FPGA-based OpenCL kernels. The experimental evaluation shows that the FD solution is very competitive in terms of performance, with a clear energy consumption advantage over the GPU solution.

The Murchison Widefield Array is a dipole-based aperture array synthesis telescope designed to operate in the 80-300 MHz frequency range. It is capable of a wide range of science investigations but is initially focused on three key science projects: detection and characterization of three-dimensional brightness temperature fluctuations in the 21 cm line of neutral hydrogen during the epoch of reionization (EoR) at redshifts from six to ten; solar imaging and remote sensing of the inner heliosphere via propagation effects on signals from distant background sources; and high-sensitivity exploration of the variable radio sky. The array design features 8192 dual-polarization broadband active dipoles, arranged into 512 ldquotilesrdquo comprising 16 dipoles each. The tiles are quasi-randomly distributed over an aperture 1.5 km in diameter, with a small number of outliers extending to 3 km. All tile-tile baselines are correlated in custom field-programmable gate array based hardware, yielding a Nyquist-sampled instantaneous monochromaticuvcoverage and unprecedented point spread function quality. The correlated data are calibrated in real time using novel position-dependent self-calibration algorithms. The array is located in the Murchison region of outback Western Australia. This region is characterized by extremely low population density and a superbly radio-quiet environment, allowing full exploitation of the instrumental capabilities.