Demo Data from SIGIR 2026 / reviewers in the wild / expert
Changping Chen
dblp:20/10037
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2018
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 61% Memory systems · 39% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing › parallel scheduling
adaptive scheduling |
0.3 | 1 | 2018 | Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies · MICRO 2018 |
Parallel and multicore computing › parallel scheduling
thread scheduling |
0.3 | 1 | 2018 | Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies · MICRO 2018 |
Memory systems › processing-in-memory
near-data processing |
0.1 | 1 | 2018 | Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies · MICRO 2018 |
Methods — techniques the papers use, named apart from their topics
performance modeling · 0.3cache partitioning algorithms · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | Adaptive Scheduling for Systems with Asymmetric Memory HierarchiesabstractConventional multicores rely on deep cache hierarchies to reduce data movement. Recent advances in die stacking have enabled near-data processing (NDP) systems that reduce data movement by placing cores close to memory. NDP cores enjoy cheaper memory accesses and are more area-constrained, so they use shallow cache hierarchies instead. Since neither shallow nor deep hierarchies work well for all applications, prior work has proposed systems that incorporate both. These asymmetric memory hierarchies can be highly beneficial, but they require scheduling computation to the right hierarchy. We present AMS, an adaptive scheduler that automatically finds high-quality thread-to-hierarchy mappings. AMS monitors threads, accurately models their performance under different hierarchies and core types, and adapts algorithms first proposed for cache partitioning to produce high-quality schedules. AMS is cheap enough to use online, so it adapts to program phases, and performs within 1% of an exhaustive-search scheduler. As a result, AMS outperforms asymmetry-oblivious schedulers by up to 37% and by 18% on average. Po-An Tsai, Changping Chen, Daniel Sánchez 0003 |
MICRO | 2 |