To overcome the difficulty in model parameter extraction and the narrow model coverage of physics-based compact models, artificial neural network-based compact models (ANN CM) have been developed. However, the ANN CM lacks physical consistency and sub-models for circuit simulations. In this work, we propose an innovative hybrid compact model that uses a physics-based compact model as a basis with accurate fitting capability over a wide range using two neural networks (NN). First, a bidirectional physics-based compact model generator neural network (PMG-NN) can automatically extract model parameter sets for both the drain current and gate capacitance within a few minutes. Second, a deep global correction neural network (DGC-NN) corrects the electrical inconsistencies caused by process variations to solve the narrow model coverage issues. The hybrid compact model (Hybrid CM) using DGC-NN can predict Ids, Cgg, Cgd, and Cgs of TCAD-simulated 3 nm nanosheet FETs (NSFETs) with greater than 98.5% accuracy. The hybrid compact model was implemented using Verilog-A and validated through the Gummel symmetry test and SPICE simulations. This new type of compact model has the potential to be the best solution for efficient process optimization and accurate SPICE simulation in real-world applications.

In this work, we propose a SoC power estimation framework built on our system-level simulation environment. Our framework provides designers with the system-level power profile in a cycle-accurate manner. We target the framework to run fast and accurately, which is enabled by adopting different modeling techniques depending on the power characteristics of various IP blocks. The framework can be applied to any target SoC design

Modern multimedia, gaming and entertainment devices epitomize high-growth, consumer-driven applications for silicon. 2006 has been a year that launched several high-profile gaming systems, and major changes in home networking. This year has also witnessed the emergence of the digital home and the ePC, as well as continued struggles for control of the home gateway. Mobile-digital has continued with the fusion of media, telephony, and digital-mobile TV. The industry's ability to rapidly evolve such consumer-centric systems brings to bear all of the technology competencies required for cutting-edge IC designs, as well as for tools and methodologies that support those designs. Multimedia and gaming chips are pushing the leading edge of EDA technology forward on fronts that include architectural synthesis, high-speed clocking, power management, verification, and IP reuse. As just one example, GPU operations per second are growing significantly faster than desktop CPU operations per second, while at the same time, GPU design teams often place less, emphasis than microprocessor teams on circuits and layout, and more emphasis on architecture and design enablement. The confluence of these trends leads to design and CAD solutions that are unique in the market space. In this panel session, the panelists have been selected to represent five key constituencies: the digital home (Intel), mobile digital TV (Samsung), graphics engines (NVIDIA), advanced displays (Pixelworks), and gaming/multimedia processing (IBM). The panel will address such questions as; what are the underlying chip architectures and roadmaps for key multimedia/entertainment platforms?; what are the key design and technology challenges (or brick walls) for next-generation products, and how will these challenges be addressed?; where will we see the next convergence in devices and platforms?; what other challenges arise from complex supplier and competitor relationships, standards, and other aspects of a globalized market? Other design challenges to be discussed include design enablement (compilers, programming models, etc.), design for IP reuse (configurability, derivatives), and IP management in a world of increasing co-opetition.

The topic on platform-based system modeling has received a great deal of attention today. One of the important tasks that significantly affect the effectiveness and efficiency of the system modeling is the modeling of IP components and communication between IPs. To be effective, it is generally accepted that the system modeling should be performed in two steps; In the first step, a fast but some inaccurate system modeling is considered to facilitate the simultaneous development of software and hardware. The second step then refines the models of the software and hardware blocks (i.e., IPs) to increase the simulation accuracy for the system performance analysis. Here, one critical factor required for a successful system modeling is a systematic modeling of the IP blocks and bus subsystem connecting the IPs. In this respect, this work addresses the problem of systematic modeling of the IPs and bus subsystem in different levels of refinements. In the experiments, we found that by applying our proposed IP and bus modeling methods to the MPEG-4 application, we are able to achieve 4/spl times/ performance improvement and at the same time, reduce the software development time by 35%, compared to that by conventional modeling methods.

We propose a new intra-task dynamic voltage scaling (DVS) method to capture an important fact of ‘software runtime distribution ’ and integrate it into DVS effectively. Specifically, the proposed method finds performance levels, for a given software runtime distribution, i.e. statistical profiling of execution cycles (neither the execution cycle of worst-case execution path nor the worst-case execution cycles of basic blocks), which leads to a minimal energy consumption while satisfying the given deadline constraints. Experimental results report that the proposed method gives 19.2%~33.3 % further energy reduction compared with the best-known methods for two industrial multimedia software programs, H.264 decoder and MPEG4 decoder. 1.

A transaction level modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented the transaction-level model of a proprietary bus called AHB+ which supports an extended AMBA2.0 protocol. The AHB+ transaction-level model is shown to be 353 times faster than the pin-accurate RTL model, while maintaining 97% accuracy on average. We also present the TLM development procedure of a bus architecture.

Summary form only given. The growth of the semiconductor industry has been driven by a series of electronic system applications (such as personal computers, home entertainment and mobile handsets), and, most recently, by the revolution of the information technology (IT) industry. The key word of this next revolution is "ubiquitous". As semiconductor technology is scaled into the nanometer regime, where hundreds of millions of transistors can be placed on a chip, designers are now incorporating their advanced system concepts into silicon. These systems include digital, analogue, and RF components. System-on-a-chip (SoC) enables the IT industry to realise various products that can comply with rapidly changing market requirements and with the unprecedented ubiquitous life style. However, SoC products in the ubiquitous era face challenges such as high performance, low-power, small-size and low-cost. These factors may jeopardise the success of SoC unless there is a breakthrough from system-level design to manufacturing technologies. Advanced EDA technology is indispensable to cope with the ever-increasing design complexity of gigascale integration and complicated physical effects inherent from the nanoscale technology. The author provides an overview of the key challenges with SoC developments, namely: issues in system-level design, low power, high performance, verification, and relevant nanometer technology. Solutions, including some of Samsung's recent R&D activities in those areas, are discussed. All of these issues challenge the endless possibilities of SoC.

For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an SoC design. Furthermore, bus IP vendors provide software tools that automatically generate RTL codes of a bus once its designer configures it. Configurability, however, imposes more challenges upon designers because complexity involved in optimization increases exponentially as the number of parameters grows. In this paper, we present a novel approach with which effort requirement can be dramatically reduced. An automated optimization tool we developed is used and it exploits a genetic algorithm for fast design exploration. This paper shows that the time for the optimizing task can be reduced by more than 90% when the tool is used and, more significantly the task can be done without an expert's hand while ending up with a better solution.

As silicon CMOS technology is scaled into the nanometer regime, the paradigm shift of computer-aided design (CAD) technology is indispensable to cope with two major challenges (i.e., the ever-increasing design complexity of gigascale integration and complicated physical effects inherent from the nanoscale technology). System-level design and verification methodologies manage the functional complexity, and manufacturing-aware design techniques control the nanoscale physical effects. In this highlight paper, most nanometer design issues are described and the issues related to the higher level of abstraction are summarized. Process variability can be controlled by statistical design, resolution enhancement, planarity control, and other manufacturing-aware design techniques. Continuously growing problems such as leakage power, signal integrity, and reliability are also discussed. Finally, technology CAD for future nanometer devices is presented. For successful nanometer silicon design, closer cooperation among the design, process technology, mask, and CAD communities are essential.

The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low Vth transistors are used to implement the desired function, the high Vth transistors are used to cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS technology for the Samsung's 0.18?m process, (ii) propose a new special flip-flop which keeps a valid data during the sleep mode, and (iii) develop a methodology which takes into account the new design issues related to the MTCMOS technology. Towards validating the proposed technique, a Personal Digital Assistant (PDA) processor has been implemented using the MTCMOS design methodology, and the 0.18?m process. The fabricated PDA processor operates at 333MHz, and consumes about 2?W of leakage power. Whereas the performance of the MTCMOS implementation is the same as that of the generic CMOS implementation, three orders of reduction in the leakage power has been achieved.

In this paper, we present CubicPower which is a dynamic power estimator based on Verilog/VHDL simulators.We propose the power characterieation model and the probablistic contribution measure(PCM) algorithm to calculate the actual power consumption of cell instances with given switching information.In addition to PCM, the state dependency and non-switching activity of gates are taken into account for more accurate power estimation.Experimental results of CubicPower show less than 10% error compared with the results of PowerMill simulation and the measured values of the IMS test equipment.Due to the PCM algorithm, CubicPower is more accurate than the leading commercial dynamic power estimator at the gate level and is 2-3 orders of magnitude faster than PowerMill.

A new approach for the statistical worst case of fall-chip circuit performance and parametric yield prediction, using both the modified-principal component analysis (MPCA) and the gradient method (GM), is proposed and verified. This method enables designers not only to predict the standard deviations of circuit performances but also track the circuit performances associated with the process shift using wafer test structure measurements. This new method is validated experimentally during the development and production of high density DRAMs.

This paper presents accurate series-transistor reduction techniques which extend the applicability of linear and nonlinear macromodels to more complex structures through accurately modeling the channel length modulation effect, effective transconductance, input terminal position dependence, parasitic capacitances, such as gate coupling capacitances, and the body effect. Adequate solutions to address these sources of delay errors have not been previously provided. Errors, if secondary effects are not addressed, may total 100% or more. The significant improvement in simulation accuracy using these proposed techniques is shown.

This paper presents new techniques for accurately accounting for RC-interconnect effects in conjunction with nonlinear MOS macromodeling. RC-interconnects contribute to the delay of signals, but more importantly, they alter the shape of signals. Thus, circuit performance is affected by nonlinear transistors, secondary MOS effects, input waveform shape, and RC-interconnect loading. All these issues are addressed by the techniques presented here. An equivalent /spl pi/-model for RC-interconnects is used in combination with advanced nonlinear MOS macromodeling to provide simulation results with accurate timing and, more critically, waveform shape of the gate output. Thus, the macromodel provides accurate simulation results whether the behavior is dominated by the nonlinear transistors or RC-interconnects. These techniques yield accurate circuit behavior at speeds two orders of magnitude faster than SPICE for even small circuits.

This paper presents accurate series-transistor reduction techniques which extend the applicability of linear and nonlinear macromodels to more complex structures through accurately modeling the channel length modulation effect, effective transconductance, input terminal position dependence, parasitic capacitances, such as gate coupling capacitances, and the body effect. Adequate solutions to address these sources of delay errors, which may total 100% or more, have not been previously provided. The significant improvement in simulation accuracy using these proposed techniques is shown. The timing macromodel used to implement these techniques is up to several hundred times faster than SPICE2 and up to several times faster than existing nonlinear macromodels. The accuracy of this macromodel over a wide range of operating conditions is demonstrated. The macromodel and reduction techniques can be used to minimize VLSI simulation time, provide fast feedback in circuit optimization, and generate accurate data for higher-level macromodels. The proposed reduction techniques apply to linear and nonlinear macromodels.>

A table look-up model for MOSFETs has been implemented into SPICE2G.6 to compute I/sub ds/ and its first-order derivatives using a three-dimensional linear isoparametric shape function. This method accurately calculates continuous and monotonic I/sub ds/ and its continuous first-order derivatives with a relatively small number of data points. As a consequence, this table look-up model converges more rapidly, compared to the analytic model of SPICE2G.6. The total number of Newton-Raphson iterations is on the average 10% less than that of SPICE2G.6 simulation.>