The authors designed a set of four ICs to provide encoding, multiplexing, clock extraction/demultiplexing, and decoding for gigabit-rate serial data transmission. These chips form a high bandwidth data link for point-to-point communication. A new line code is implemented that provides DC balance, efficient encoding, framing, and simple clock extraction. Embedded in the code is a fixed transition used by the phase/frequency locked loop (PLL) for simple clock extraction and frame synchronization. Unlike other links, this PLL requires no trimming for data retiming, either in production or later. An on-chip voltage-controlled oscillator (VCO) with a tuning range of 1.1-1.6 GHz is available for use with the PLL. With this chip set the authors demonstrated a transmission rate of 16 bits in parallel at 75 MHz or, with encoding overhead, a serial rate of 1.5 Gb/s.>

This paper describes system and circuit considerations for transmit/receive integrated circuits meeting the requirements of industrial fiber optic data links. The integrated circuits are: TTL compatible, operate with arbitrary data format over the range from d.c. to a maximum NRZ data rate of 15 Mbits/s with a 10-9error rate at a minimum receiver detector current of 125 nA, have >55 dB electrical dynamic range and an automatic link monitor, operate from a single +5 V supply and are temperature and voltage compensated. These circuits utilize an internal pulse bipolar line coding to accommodate an arbitrary input signal format or, by switching a control input, an ON-OFF modulation for zero average TTL input signals operating above 2 Mbit/s data rate.