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Naji Naufel

dblp:20/909 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2001
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Software-defined and programmable networks · 87% Routing and switching · 13%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 100%

Topics — the 2 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Software-defined and programmable networks › programmable data plane
FPGA-based packet processing		 0.012001
Reprogrammable network packet processing on the field programmable port extender (FPX) · FPGA 2001
Software-defined and programmable networks
programmable data plane		 0.012001
Reprogrammable network packet processing on the field programmable port extender (FPX) · FPGA 2001

Methods — techniques the papers use, named apart from their topics

dynamic module loading · 0.1
YearPublicationVenuePosition
2001 Reprogrammable network packet processing on the field programmable port extender (FPX)
abstract
A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the Field Programmable Port Extender (FPX), enables packet processing functions to be implemented as modular components in reprogrammable hardware. All logic on the on the FPX is implemented in two Field Programmable Gate Arrays (FPGAs). Packet processing functions in the system are implemented as dynamically-loadable modules.
John W. Lockwood, Naji Naufel, Jonathan S. Turner, David E. Taylor
 FPGA2