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Xiaohe Cheng

dblp:202/1152 · DBLP profile ↗
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4ranked-venue papers
0as first author
0since 2021 · last 2020
0000-0001-9420-778XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 2Systems, architecture and hardware · 1Computer networks · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Performance modeling and evaluation · 26% Reconfigurable computing and FPGAs · 23% Cloud and datacenter computing · 23%
Computer networks
1 paper
Physical-layer communications · 50% Cellular and mobile networks · 50%
Software engineering, system software, and programming languages
1 paper
Concurrent programming · 100%

Topics — the 10 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA virtualization
0.412020
A Hypervisor for Shared-Memory FPGA Platforms · ASPLOS 2020
Cloud and datacenter computing
virtualization
0.412020
A Hypervisor for Shared-Memory FPGA Platforms · ASPLOS 2020
Concurrent programming
synchronization
0.412019
Scalable and practical locking with shuffling · SOSP 2019
Performance modeling and evaluation › parallel performance evaluation
multicore scalability
0.412019
Scalable and practical locking with shuffling · SOSP 2019
Parallel and multicore computing › synchronization
NUMA-aware locking
0.412019
Scalable and practical locking with shuffling · SOSP 2019
Cellular and mobile networks
5g
0.312017
Wideband Circularly Polarized Antipodal Curvedly Tapered Slot Antenna Array for 5G Applications · IEEE J. Sel. Areas Commun. 2017
Physical-layer communications
antenna arrays
0.312017
Wideband Circularly Polarized Antipodal Curvedly Tapered Slot Antenna Array for 5G Applications · IEEE J. Sel. Areas Commun. 2017
Physical-layer communications
antenna design
0.312017
Wideband Circularly Polarized Antipodal Curvedly Tapered Slot Antenna Array for 5G Applications · IEEE J. Sel. Areas Commun. 2017
Cellular and mobile networks
millimeter-wave communication
0.312017
Wideband Circularly Polarized Antipodal Curvedly Tapered Slot Antenna Array for 5G Applications · IEEE J. Sel. Areas Commun. 2017
Hardware accelerators and domain-specific architectures › accelerator orchestration
accelerator sharing
0.112020
A Hypervisor for Shared-Memory FPGA Platforms · ASPLOS 2020

Methods — techniques the papers use, named apart from their topics

page table slicing · 0.4multiplexer tree · 0.4accelerator preemption · 0.4substrate-integrated waveguide · 0.3
YearPublicationVenuePosition
2020 A Hypervisor for Shared-Memory FPGA Platforms
abstract
Cloud providers widely deploy FPGAs as application-specific accelerators for customer use. These providers seek to multiplex their FPGAs among customers via virtualization, thereby reducing running costs. Unfortunately, most virtualization support is confined to FPGAs that expose a restrictive, host-centric programming model in which accelerators cannot issue direct memory accesses (DMAs). The host-centric model incurs high runtime overhead for workloads that exhibit pointer chasing. Thus, FPGAs are beginning to support a shared-memory programming model in which accelerators can issue DMAs. However, virtualization support for shared-memory FPGAs is limited. This paper presents Optimus, the first hypervisor that supports scalable shared-memory FPGA virtualization. Optimus offers both spatial multiplexing and temporal multiplexing to provide efficient and flexible sharing of each accelerator on an FPGA. To share the FPGA-CPU interconnect at a high clock frequency, Optimus implements a multiplexer tree. To isolate each guest's address space, Optimus introduces the technique of page table slicing as a hardware-software co-design. To support preemptive temporal multiplexing, Optimus provides an accelerator preemption interface. We show that Optimus supports eight physical accelerators on a single FPGA and improves the aggregate throughput of twelve real-world benchmarks by 1.98x-7x.
Jiacheng Ma 0001, Gefei Zuo, Kevin Loughlin, Xiaohe Cheng, Yanqiang Liu, Abel Mulugeta Eneyew, Zhengwei Qi, Baris Kasikci
ASPLOS4
2020 Analysis and design of novel wideband and high efficiency millimeter-wave antenna arrays for 60-GHz applications
abstract
A type of millimeter-wave antenna array with flexible design is proposed for a variety of applications at 60 GHz. The antenna array can be adjusted to be linearly or circularly polarized by simply changing the radiation part of the antenna array. High gain, wideband, and high radiation efficiency characteristics can be achieved by adopting a low insertion loss feeding network and broadband antenna elements. For the linearly polarized antenna array, simulation results show that the impedance bandwidth of the 2×2 antenna subarray reaches 21.6%, while the maximum gain achieves 15.1 dBi and has a fluctuation of less than 0.4 dBi within the working bandwidth. Simulation results of the 8×8 linearly polarized antenna array show a bandwidth of 21.6% and a gain of (26.1±1) dBi with an antenna efficiency of more than 80%. For the 8×8 circularly polarized antenna array, simulation results show that an impedance bandwidth of 18.2% and an axial ratio (AR) bandwidth of 13.3% are obtained. Gain and efficiency of up to 27.6 dBi and 80% are achieved, respectively. A prototype of antenna array is fabricated, and results are compared and analyzed.
Kai-lai Wu, Yuan Yao 0003, Xiaohe Cheng, Junsheng Yu, Xiaodong Chen 0001
Frontiers Inf. Technol. Electron. Eng.3
2019 Scalable and practical locking with shuffling
abstract
Locks are an essential building block for high-performance multicore system software. To meet performance goals, lock algorithms have evolved towards specialized solutions for architectural characteristics (e.g., NUMA). However, inpractice, applications run on different server platforms and exhibit widely diverse behaviors that evolve with time (e.g., number of threads, number of locks). This creates performance and scalability problems for locks optimized for a single scenario and platform. For example, popular spinlocks suffer from excessive cache-line bouncing in NUMA systems, while scalable, NUMA-aware locks exhibit sub-par single-thread performance.
Sanidhya Kashyap, Irina Calciu, Xiaohe Cheng, Changwoo Min, Taesoo Kim
SOSP3
2017 Wideband Circularly Polarized Antipodal Curvedly Tapered Slot Antenna Array for 5G Applications
abstract
This paper presents and characterizes a novel high gain circularly polarized (CP) antenna array for 5G applications. The array element is an antipodal curvedly tapered slot antenna (ACTSA) generating circularly polarized field. The CP ACTSA fed by substrate integrated waveguide (SIW) is convenient to integrate with substrates. By introducing two sheet metals on the two sides of the rectangular Rogers 6002 substrate, an impedance bandwidth of 18.2%, a wide 3-dB axial ratio (AR) bandwidth of 16.9%, and stable gain of 8 ± 0.6 dBic over the operating band are achieved. By employing the proposed CP ACTSA as radiating elements, a 4 × 4 high-gain wideband antenna array is proposed for 5G E-band and W-band millimeter-wave applications. Fabrications are carried out using wire cutting electrical discharge machine and print circuit board process, which have advantages of low cost. The whole feeding network is realized by SIW with low insertion loss at millimeter-wave band. Benefiting from the wide impedance and AR bandwidth of the new antenna element, good impedance matching and AR characteristics can be achieved over the whole working frequency band from 81 to 95 GHz by this antenna array. Gain up to 18.5 ± 1.3 dBic is also obtained.
Yuan Yao 0003, Xiaohe Cheng, Chaowei Wang, Junsheng Yu, Xiaodong Chen 0001
IEEE J. Sel. Areas Commun.2