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Armando Conci

dblp:202/3313 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2009
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 65% Integrated circuit design · 26% Memory systems · 5%

Topics — the 6 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
design methodology
0.012003
Current criticalities and innovation perspectives in flash memory design automation · Proc. IEEE 2003
Integrated circuit design › analog and mixed-signal circuits
mixed-signal circuit design
0.012003
Current criticalities and innovation perspectives in flash memory design automation · Proc. IEEE 2003
Electronic design automation
physical design
0.012003
Current criticalities and innovation perspectives in flash memory design automation · Proc. IEEE 2003
Integrated circuit design › packaging
system-in-package
0.012009
System in Package Feasibility Process · Proc. IEEE 2009
Storage systems › flash and SSD
flash memory
0.012003
Current criticalities and innovation perspectives in flash memory design automation · Proc. IEEE 2003
Memory systems
non-volatile memory
0.012003
Current criticalities and innovation perspectives in flash memory design automation · Proc. IEEE 2003

Methods — techniques the papers use, named apart from their topics

electrical analysis · 0.1design process verification · 0.1statistical analog circuit simulation · 0.0
YearPublicationVenuePosition
2009 System in Package Feasibility Process
abstract
This paper describes the procedure and the software process to verify the feasibility of a system in package. The process has been created to guarantee and ensure the main characteristics of such devices: a minimum time-to-market and great flexibility. A procedure is described for every step, starting from application definition to final electrical analysis. After a general introduction, all process design steps are technically analyzed; then each step of the final process check is described. Some comments and wishes are discussed in the conclusion.
Pier Paolo Stoppino, Armando Conci, Tito Lessio, Davide Ferrara
Proc. IEEE2
2003 Current criticalities and innovation perspectives in flash memory design automation
abstract
With reference to technological, architectural, and market considerations, the specific areas of design methodology and automation in flash memory design are analyzed in this paper. For each of the activities identified as critical, we show the design process key constraints and specifications, which drive the change in methodology, tools, and flows. We go through a brief survey of the solutions adopted in the recent past as well as the new emerging areas of intervention. The analysis covers: 1) design methodology, floorplanning, full-custom layout design and Rtl2Layout automation integration; 2) analog-digital mixed full-chip simulation and architectural exploration; 3) statistical analog circuital simulation; 4) mixed-signal design to test approaches; and 5) IC and package design integration.
Armando Conci, Anna Faldarini, Gaspare Fumagalli, Antonio Girardi, Maecello Pesare, Nicola Tecli, Massiomo Zucchinali
Proc. IEEE1