Demo Data from SIGIR 2026 / reviewers in the wild / expert
Tin-Yin Lai
dblp:202/9671
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 2018
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
logic synthesis |
0.3 | 1 | 2017 | LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs · DAC 2017 |
Electronic design automation
timing analysis |
0.3 | 1 | 2017 | LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs · DAC 2017 |
Electronic design automation › logic synthesis › performance-driven synthesis
timing-driven synthesis |
0.3 | 1 | 2017 | LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs · DAC 2017 |
Electronic design automation › timing analysis › timing model
timing macro modeling |
0.3 | 1 | 2017 | LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs · DAC 2017 |
Methods — techniques the papers use, named apart from their topics
tree-based graph reduction · 0.3multithreading · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | A highly compressed timing macro-modeling algorithm for hierarchical and incremental timing analysisabstractLarge-scale hierarchical and incremental timing analysis has driven the need for highly compressed timing macro-models. A small timing macro-model for accelerating hierarchical timing is desired because the size of incremental changes dramatically increases as the macro-models are widely used in the large design process. In fact, it takes days for an incremental timing analysis on millions of gates with thousands of incremental changes. To date, the timing macro-models generated by timing macro-modeling algorithms from all the previous works are not compact enough. In this work, we provide four essential techniques in our timing macro-modeling algorithm, which are able to generate highly compressed timing macro-models for hierarchical and incremental timing analysis. In addition, our timing macro-model maintain high accuracy and the efficiency in generating our macro-models. Our algorithm generates timing macro-models where the model sizes are 9% better in the number of nodes and 19% better in the number of edges than the original circuit. Our work outperforms the state of arts significantly in both model size and the runtime in macro-model usage. Tin-Yin Lai, Martin D. F. Wong |
ASP-DAC | 1 |
| 2017 | LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical DesignsabstractThe ever-increasing design complexity is driving the need of fast and accurate macro-modeling algorithms to accelerate the hierarchical timing. We introduce LibAbs, an effective macro-modeling algorithm that efficiently supports high accuracy, high compression rate, and multi-threading. LibAbs applies tree-based graph reduction techniques to reduce the model size with comparable accuracy values to the flat model under multi-threaded environment. LibAbs outperforms existing tools including top winners from TAU 2016 macro-modeling contest in terms of model size, accuracy, and runtime on industry benchmarks. The in-context usage of our abstracted model has also demonstrated promising performance for timing-driven optimizations in large hierarchical designs. Tin-Yin Lai, Tsung-Wei Huang, Martin D. F. Wong |
DAC | 1 |