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Redha Gouicem

dblp:204/3799 · DBLP profile ↗
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10ranked-venue papers
2as first author
5since 2021 · last 2026
0000-0003-4619-5221ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 7 · 2 first-author · 4 since 2021Software engineering, systems software and programming languages · 5 · 1 first-author · 3 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
8 papers
Concurrent programming · 44% Runtime systems and virtual machines · 28% Operating systems · 24%
Computer architecture, parallel and distributed computing, and storage systems
7 papers
Cloud and datacenter computing · 32% Parallel and multicore computing · 31% Processor architecture and microarchitecture · 17%

Topics — the 16 heaviest of 18, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Concurrent programming
memory models
2.232026
Arancini: A Hybrid Binary Translator for Weak Memory Model Architectures · ASPLOS (2) 2026
Risotto: A Dynamic Binary Translator for Weak Memory Model Architectures · ASPLOS (1) 2023
Lasagne: a static binary translator for weak memory model architectures · PLDI 2022
Concurrent programming › memory models
weak memory models
2.232026
Arancini: A Hybrid Binary Translator for Weak Memory Model Architectures · ASPLOS (2) 2026
Risotto: A Dynamic Binary Translator for Weak Memory Model Architectures · ASPLOS (1) 2023
Lasagne: a static binary translator for weak memory model architectures · PLDI 2022
Runtime systems and virtual machines
binary translation
1.622026
Arancini: A Hybrid Binary Translator for Weak Memory Model Architectures · ASPLOS (2) 2026
Lasagne: a static binary translator for weak memory model architectures · PLDI 2022
Operating systems › resource management › process management
CPU scheduling
1.232020
Fewer Cores, More Hertz: Leveraging High-Frequency Cores in the OS Scheduler for Improved Application Performance · USENIX ATC 2020
Provable multicore schedulers with Ipanema: application to work conservation · EuroSys 2020
The Battle of the Schedulers: FreeBSD ULE vs. Linux CFS · USENIX ATC 2018
Operating systems › i/o › i/o subsystem
i/o buffering and caching
1.012026
PaCaR: Improved Buffered I/O Locality on NUMA Systems with Page Cache Replication · EuroSys 2026
Parallel and multicore computing › multiprocessor system › distributed-memory multiprocessor
NUMA systems
1.012026
PaCaR: Improved Buffered I/O Locality on NUMA Systems with Page Cache Replication · EuroSys 2026
Runtime systems and virtual machines › binary translation
dynamic binary translation
0.712023
Risotto: A Dynamic Binary Translator for Weak Memory Model Architectures · ASPLOS (1) 2023
Runtime systems and virtual machines › binary translation
static binary translation
0.612022
Lasagne: a static binary translator for weak memory model architectures · PLDI 2022
Cloud and datacenter computing › virtualization › lightweight virtualization
lightweight virtual machines
0.612022
VMSH: hypervisor-agnostic guest overlays for VMs · EuroSys 2022
Cloud and datacenter computing
virtualization
0.612022
VMSH: hypervisor-agnostic guest overlays for VMs · EuroSys 2022
Processor architecture and microarchitecture
instruction set architecture
0.522026
Arancini: A Hybrid Binary Translator for Weak Memory Model Architectures · ASPLOS (2) 2026
Risotto: A Dynamic Binary Translator for Weak Memory Model Architectures · ASPLOS (1) 2023
High-performance computing
i/o intensive applications
0.312026
PaCaR: Improved Buffered I/O Locality on NUMA Systems with Page Cache Replication · EuroSys 2026
Memory systems › cache management › storage caching
page cache
0.312026
PaCaR: Improved Buffered I/O Locality on NUMA Systems with Page Cache Replication · EuroSys 2026
Operating systems
virtualization
0.212022
VMSH: hypervisor-agnostic guest overlays for VMs · EuroSys 2022
Processor architecture and microarchitecture
multicore design
0.112020
Fewer Cores, More Hertz: Leveraging High-Frequency Cores in the OS Scheduler for Improved Application Performance · USENIX ATC 2020
Performance modeling and evaluation
benchmarking
0.112018
The Battle of the Schedulers: FreeBSD ULE vs. Linux CFS · USENIX ATC 2018

Methods — techniques the papers use, named apart from their topics

thread migration · 2.0page cache replication · 2.0memory migration · 2.0dynamic binary translation · 1.3file system image attachment · 1.1container-based isolation · 1.1formal verification · 0.9
YearPublicationVenuePosition
2026 Arancini: A Hybrid Binary Translator for Weak Memory Model Architectures
abstract
Binary translation is a powerful approach to support cross-architecture emulation of unmodified binaries in increasingly heterogeneous computing environments. However, binary translation systems face correctness issues, due to the strong-on-weak memory model mismatch (e.g., from x86-64 to Arm/RISC-V) for concurrent programs. Besides, the current landscape of binary translation systems is fundamentally limited in terms of completeness for static systems and performance for dynamic ones.
Sebastian Reimers, Dennis Sprokholt, Martin Fink 0004, Theofilos Augoustis, Simon Kammermeier, Rodrigo Caetano Rocha, Tom Spink, Redha Gouicem, Soham Chakraborty 0001, Pramod Bhatotia
ASPLOS (2)8
2026 PaCaR: Improved Buffered I/O Locality on NUMA Systems with Page Cache Replication
abstract
Modern systems featuring multiple sockets suffer from the non-uniformity of performance of their memory accesses. Accessing memory of a remote node can lead to doubled latencies and halved bandwidth. This is particularly critical for I/O-intensive applications relying on the Linux page cache, where locality is paramount. Existing solutions migrating threads or memory across nodes fail to address the issue with highly parallel workloads, where a small working set is constantly accessed by multiple threads across nodes.
Jérôme Coquisart, Julien Sopena, Redha Gouicem
EuroSys3
2023 Risotto: A Dynamic Binary Translator for Weak Memory Model Architectures
abstract
Dynamic Binary Translation (DBT) is a powerful approach to support cross-architecture emulation of unmodified binaries. However, DBT systems face correctness and performance challenges, when emulating concurrent binaries from strong to weak memory consistency architectures. As a matter of fact, we report several translation errors in QEMU, when emulating x86 binaries on Arm hosts.
Redha Gouicem, Dennis Sprokholt, Jasper Ruehl, Rodrigo Caetano Rocha, Tom Spink, Soham Chakraborty 0001, Pramod Bhatotia
ASPLOS (1)1
2022 VMSH: hypervisor-agnostic guest overlays for VMs
abstract
Lightweight virtual machines (VMs) are prominently adopted for improved performance and dependability in cloud environments. To reduce boot up times and resource utilisation, they are usually "pre-baked" with only the minimal kernel and userland strictly required to run an application. This introduces a fundamental trade-off between the advantages of lightweight VMs and available services within a VM, usually leaning towards the former. We propose VMSH, a hypervisor-agnostic abstraction that enables on-demand attachment of services to a running VM---allowing developers to provide minimal, lightweight images without compromising their functionality. The additional applications are made available to the guest via a file system image. To ensure that the newly added services do not affect the original applications in the VM, VMSH uses lightweight isolation mechanisms based on containers. We evaluate VMSH on multiple KVM-based hypervisors and Linux LTS kernels and show that: (i) VMSH adds no overhead for the applications running in the VM, (ii) de-bloating images from the Docker registry can save up to 60% of their size on average, and (iii) VMSH enables cloud providers to offer services to customers, such as recovery shells, without interfering with their VM's execution.
Jörg Thalheim, Peter Okelmann, Harshavardhan Unnibhavi, Redha Gouicem, Pramod Bhatotia
EuroSys4
2022 Lasagne: a static binary translator for weak memory model architectures
abstract
The emergence of new architectures create a recurring challenge to ensure that existing programs still work on them. Manually porting legacy code is often impractical. Static binary translation (SBT) is a process where a program’s binary is automatically translated from one architecture to another, while preserving their original semantics. However, these SBT tools have limited support to various advanced architectural features. Importantly, they are currently unable to translate concurrent binaries. The main challenge arises from the mismatches of the memory consistency model specified by the different architectures, especially when porting existing binaries to a weak memory model architecture.
Rodrigo Caetano Rocha, Dennis Sprokholt, Martin Fink 0004, Redha Gouicem, Tom Spink, Soham Chakraborty 0001, Pramod Bhatotia
PLDI4
2020 Provable multicore schedulers with Ipanema: application to work conservation
abstract
Recent research and bug reports have shown that work conservation, the property that a core is idle only if no other core is overloaded, is not guaranteed by Linux's CFS or FreeBSD's ULE multicore schedulers. Indeed, multicore schedulers are challenging to specify and verify: they must operate under stringent performance requirements, while handling very large numbers of concurrent operations on threads. As a consequence, the verification of correctness properties of schedulers has not yet been considered.
Baptiste Lepers, Redha Gouicem, Damien Carver, Jean-Pierre Lozi, Nicolas Palix, Maria-Virginia Aponte, Willy Zwaenepoel, Julien Sopena, Julia Lawall, Gilles Muller
EuroSys2
2020 Fewer Cores, More Hertz: Leveraging High-Frequency Cores in the OS Scheduler for Improved Application Performance
Redha Gouicem, Damien Carver, Jean-Pierre Lozi, Julien Sopena, Baptiste Lepers, Willy Zwaenepoel, Nicolas Palix, Julia Lawall, Gilles Muller
USENIX ATC1
2019 Fork/Wait and Multicore Frequency Scaling: a Generational Clash
abstract
The complexity of computer architectures has risen since the early years of the Linux kernel: Simultaneous Multi-Threading (SMT), multicore processing, and frequency scaling with complex algorithms such as Intel® Turbo Boost have all become omnipresent. In order to keep up with hardware innovations, the Linux scheduler has been rewritten several times, and many hardware-related heuristics have been added. Despite this, we show in this paper that a fundamental problem was never identified: the POSIX process creation model, i.e., fork/wait, can behave inefficiently on current multicore architectures due to frequency scaling. We investigate this issue through a simple case study: the compilation of the Linux kernel source tree. To do this, we develop SchedLog, a low-overhead scheduler tracing tool, and SchedDisplay, a scriptable tool to graphically analyze SchedLog's traces efficiently.
Damien Carver, Redha Gouicem, Jean-Pierre Lozi, Julien Sopena, Baptiste Lepers, Willy Zwaenepoel, Nicolas Palix, Julia Lawall, Gilles Muller
PLOS@SOSP2
2018 The Battle of the Schedulers: FreeBSD ULE vs. Linux CFS
Justinien Bouron, Sebastien Chevalley, Baptiste Lepers, Willy Zwaenepoel, Redha Gouicem, Julia Lawall, Gilles Muller, Julien Sopena
USENIX ATC5
2017 Towards Proving Optimistic Multicore Schedulers
abstract
Operating systems have been shown to waste machine resources by leaving cores idle while work is ready to be scheduled. This results in suboptimal performance for user applications, and wasted power.
Baptiste Lepers, Willy Zwaenepoel, Jean-Pierre Lozi, Nicolas Palix, Redha Gouicem, Julien Sopena, Julia Lawall, Gilles Muller
HotOS5