This paper presents an analog-assisted hybrid low-dropout regulator (LDO) with a wide load current range and fast transient response. The proposed design is composed of digital and analog loops of which the transient response is dictated by the digital portion. A fast approximation algorithm leveraging charge distribution reduces settling time significantly compared to linear and SAR approaches. A wide load range droop detector further improves transient response with negligible power overhead. The analog assisted circuits continuously provide current in response to the load current change without disturbing the loop dynamic. Implemented in a TSMC 180-nm standard CMOS technology, the LDO supports a 430 mA maximum load and ensures loop stability without external capacitors. It achieves a 480 mV undershoot at 430 mA with 100 ns edge time,$49~\mu $A quiescent current, and settling times of 225 ns and 260 ns for undershoot and overshoot at$C_{L}=0$pF when a 10-MHz clock is used. Measurement shows that activating the droop detector reduces undershoot by 54%.

This paper presents a high-speed low dropout (LDO) regulator with wide dynamic range. The use of piecewise speed enhancement technique dividing the loop dynamic into three phases in which the current regulation circuits (CRC), large-signal derivative path control circuits addressing the design challenge of slew rate limitation, and the hybrid passive-active frequency compensation (PAFC) for small signal settling time improvements are introduced lends the proposed LDO to providing constant output voltage under the condition of large load variations. The LDO is designed in TSMC 180-nm 1.8 V standard CMOS technology with 0.17 mm2 active area. The quiescent current is 380$\mu \mathrm{A}$at no load. With regulated 1.2 V output, the input voltage ranges from 1.3 V to 1.8 V. The measured overshoot and undershoot with load steps of 0 to 100 mA at 50 ns edge time are 135 mV and 105 mV, respectively. The settling time at 25 mA, 50 mA and 100 mA are 2.6$\mu \mathrm{s}, 4.5\mu \mathrm{s}$, and 9.8$\mu \mathrm{s}$, respectively. The LDO is competent in handling a wide range of output capacitance from 0 to 5 nF while the overshoot and undershoot exhibits small variation in the load step response.

Maintenance is recognised as the most difficult and expansive activity of the software development process. Numerous techniques and processes have been proposed to ease the maintenance of software. In particular, several authors published design defects formalising "bad" solutions to recurring design problems (e.g., anti-patterns, code smells). We propose a language and a framework to express design defects synthetically and to generate detection algorithms automatically. We show that this language is sufficient to describe some design defects and to generate detection algorithms, which have a good precision. We validate the generated algorithms on several programs