We introduce an adaptive level-of-detail technique for ray tracing triangle meshes that aims to reduce the memory bandwidth used during ray traversal, which can be the bottleneck for rendering time with large scenes and the primary consumer of energy. We propose a specific data structure for hierarchically representing triangle meshes, allowing localized decisions for the desired mesh resolution per ray. Starting with the lowest-resolution triangle mesh level, higher-resolution levels are generated by tessellating each triangle into four via splitting its edges with arbitrarily-placed vertices. We fit the resulting mesh hierarchy into a specialized acceleration structure to perform on-the-fly tessellation level selection during ray traversal. Our structure reduces both storage cost and data movement during rendering, which are the main consumers of energy. It also allows continuous transitions between detail levels, while locally adjusting the mesh resolution per ray and preserving watertightness. We present how this structure can be used with both primary and secondary rays for reflections and shadows, which can intersect with different tessellation levels, providing consistent results. We also propose specific hardware units to cover the cost of additional compute needed for level-of-detail operations. We evaluate our method using a cycle-accurate simulation of a custom ray tracing hardware architecture. Our results show that, as compared to traditional bounding volume hierarchies, our method can provide more than an order of magnitude reduction in energy use and render time, given sufficient computational resources.

Mesh Colors provide an effective alternative to standard texture mapping. They significantly simplify the asset production pipeline by removing the need for defining a mapping and eliminate rendering artifacts due to seams. This article addresses the problem that using Mesh Colors for real-time rendering has not been practical, due to the absence of hardware support. We show that it is possible to provide full hardware texture filtering support for Mesh Colors with minimal changes to existing GPUs by introducing a hardware-friendly representation for Mesh Colors that we call Patch Textures, which can have quadrilateral or triangular topology. We discuss the hardware modifications needed for storing and filtering Patch Textures, including anisotropic filtering. This article extends our previous work by discussing and comparing patch edge-handling approaches, including an option for sampling the textures of neighboring patches using an adjacency map. We also provide extensive discussions regarding data duplication, a partial implementation present in existing hardware, and the difficulties with providing a similar hardware support for Ptex.

Abstract Interpolation is a core operation that has widespread use in computer graphics. Though higher‐order interpolation provides better quality, linear interpolation is often preferred due to its simplicity, performance, and hardware support. We present a unified refactoring of quadratic and cubic interpolations as standard linear interpolation plus linear interpolations of higher‐order terms and show how they can be applied to regular grids and (triangular/tetrahedral) simplexes Our formulations can provide significant reduction in computation cost, as compared to typical higher‐order interpolations and prior approaches that utilize existing hardware linear interpolation support to achieve higher‐order interpolation. In addition, our formulation allows approximating the results by dynamically skipping some higher order terms with low weights for further savings in both computation and storage. Thus, higher‐order interpolation can be performed adaptively, as needed. We also describe how relatively minor modifications to existing GPU hardware could provide hardware support for quadratic and cubic interpolations using our approach for both texture filtering operations and barycentric interpolation. We present a variety of examples using triangular, rectangular, tetrahedral, and cuboidal interpolations, showing the effectiveness of our higher‐order interpolations in different applications.

We describe how to modify hardware page translation to enable CPU software access to compressed and swizzled GPU data arrays as if they were decompressed and stored in row-major order. In a shared memory system, this allows CPU to directly access the GPU data without copying the data or losing the performance and bandwidth benefits of using compression and swizzling on the GPU.

Medical volumetric imaging requires high fidelity, high performance rendering algorithms. We motivate and analyze new volumetric rendering algorithms that are suited to modern parallel processing architectures. First, we describe the three major categories of volume rendering algorithms and confirm through an imaging scientist-guided evaluation that ray-casting is the most acceptable. We describe a thread- and data-parallel implementation of ray-casting that makes it amenable to key architectural trends of three modern commodity parallel architectures: multi-core, GPU, and an upcoming many-core Intel architecture code-named Larrabee. We achieve more than an order of magnitude performance improvement on a number of large 3D medical datasets. We further describe a data compression scheme that significantly reduces data-transfer overhead. This allows our approach to scale well to large numbers of Larrabee cores.

This paper presents a many-core visual computing architecture code named Larrabee, a new software rendering pipeline, a manycore programming model, and performance analysis for several applications. Larrabee uses multiple in-order x86 CPU cores that are augmented by a wide vector processor unit, as well as some fixed function logic blocks. This provides dramatically higher performance per watt and per unit of area than out-of-order CPUs on highly parallel workloads. It also greatly increases the flexibility and programmability of the architecture as compared to standard GPUs. A coherent on-die 2 nd level cache allows efficient inter-processor communication and high-bandwidth local data access by CPU cores. Task scheduling is performed entirely with software in Larrabee, rather than in fixed function logic. The customizable software graphics rendering pipeline for this architecture uses binning in order to reduce required memory bandwidth, minimize lock contention, and increase opportunities for parallelism relative to standard GPUs. The Larrabee native programming model supports a variety of highly parallel applications that use irregular data structures. Performance analysis on those applications demonstrates Larrabee's potential for a broad range of parallel computation.

This paper describes shear-image order ray casting, a new method for volume rendering. This method renders sampled data in three dimensions with image quality equivalent to the best of ray-per-pixel volume rendering algorithms (full image order), while at the same time retaining computational complexity and spatial coherence near to that of the fastest known algorithm (shear-warp). In shear-image order, as in shear-warp, the volume data set is resampled along slices parallel to a face of the volume. Unlike shear-warp, but like the texture-based methods, rays are cast through the centers of pixels of the image plane and sample points are at the intersections of rays with each slice. As a result, no post-warp step is required. Unlike texture methods, which realize shear and warp by transformations in a commodity graphics system, the shear-image ray casting methods use a new factorization that preserves memory and interpolation efficiency. In addition, a method is provided for accurately and efficiently embedding conventional polygon graphics and other objects into volumes. Both opaque and translucent polygons are supported.We also describe a method, included in shear-image order but applicable to other algorithms, for rendering anisotropic and sheared volume data sets directly with correct lighting.The shear-image order method has been implemented in the VolumeProTM 1000, a single chip real-time volume rendering engine capable of processing volume data at a pipeline rate of 109 samples per second. Figure 1 on the color page shows a shear-image order gallery of volumes rendered with different translucency, lighting, and some embedded geometry.

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A well-integrated chip-to-system design for test strategy and its implementation in a set of custom VLSI video chips are discussed. It supports both chip- and board-level testing of digital and analog circuits within the video subsystem. This test strategy permits testing of critical nodes inside the custom chips, making possible many tests that could not be performed with external test logic. The test coverage achieved eliminates the need for a bed-of-nails module tester. Test generation is very simple and test time is reduced by several orders of magnitude over previously used test methods. The method is cost effective, adding only 5% to the area of each chip.>

This paper describes an architecture for design rule checking that uses a small amount of special purpose hardware to achieve a significant speed improvement over conventional methods. A fixed grid raster scan algorithm is used that allows checking of 45° angled edges at a modest cost in performance. Operations implemented directly in hardware include width checks, edge condition checks, boolean operations on masks, and shrinking and expansion of masks. Hardware support for rasterization is also provided. Software in a controlling processor handles all geometric data manipulation. This architecture should be able to check a simple set of design rules on a 300 mil square layout in one and one half minutes, if the controlling processor can provide data quickly enough. Layouts have been completed for two of four custom chips used in this architecture, and one has been fabricated and proven functional.