Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from SIGIR 2026 / reviewers in the wild / expert

Prasanti Uppaluri

dblp:21/5409 · DBLP profile ↗
← Back
3ranked-venue papers
1as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test		 0.021995
NEST: a nonenumerative test generation method for path delay faults in combinational circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995
NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits · DAC 1993
Electronic design automation › hardware verification and test
test generation		 0.021995
NEST: a nonenumerative test generation method for path delay faults in combinational circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995
NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits · DAC 1993
Electronic design automation › hardware verification and test › delay fault testing
path delay fault		 0.011995
NEST: a nonenumerative test generation method for path delay faults in combinational circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1995
Electronic design automation › hardware verification and test › test generation › fault test generation
path delay fault test generation		 0.011993
NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits · DAC 1993

Methods — techniques the papers use, named apart from their topics

non-enumerative fault targeting · 0.0
YearPublicationVenuePosition
1996 On minimizing the number of test points needed to achieve complete robust path delay fault testability
abstract
Recently, Pomeranz and Reddy (1994), presented a test point insertion method to improve path delay fault testability in large combinational circuits. A test application scheme was developed that allows test points to be utilized as primary inputs and primary outputs during testing. The placement of test points was guided by the number of paths and was aimed at reducing this number. Indirectly, this approach achieved complete robust path delay fault testability in very low computation times. In this paper, we use their test application scheme, however, we use more exact measures for guiding test point insertion like test generation and RD fault identification. Thus, we reduce the number of test points needed to achieve complete testability by ensuring that test points are inserted only on paths associated with path delay faults that are necessary to be tested and that are not robustly testable. Experimental results show that an average reduction of about 70% in the number of test points over the approach of Pomeranz and Reddy can be obtained.
Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz
 VTS1
1995 NEST: a nonenumerative test generation method for path delay faults in combinational circuits
abstract
A test generation procedure for path delay faults is proposed that targets all path delay faults in the circuit-under-test. The procedure overcomes the difficulties in handling the exorbitant numbers of path delay faults in practical circuits by using a nonenumerative method of considering faults that never explicitly targets any specific path delay fault. Experimental results demonstrate the effectiveness of the method in deriving tests to detect very large numbers of path delay faults.
Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
1993 NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits
abstract
A test generation procedure for path delay faults is proposed, that targets cdl path delay faults in the circuit-under-test.The procedure overcomes the difficulties in handling the exorbitant numbers of path delay faults in practical circuits by using a nonennmerative method of considering faults, i.e., it never explicitly targeta any specific path delay fault.Experimental results demonstrate the effectiveness of the method in deriving tests to detect very large numbers of path delay faults in short run times.
Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri
 DAC3