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Xufeng Yang

dblp:210/0416 · DBLP profile ↗
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3ranked-venue papers
2as first author
3since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021Software engineering, systems software and programming languages · 2 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Storage systems · 70% Memory systems · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache design
1.012026
Nemo: A Low-Write-Amplification Cache for Tiny Objects on Log-Structured Flash Devices · ASPLOS (2) 2026
Storage systems
flash and SSD
1.012026
Nemo: A Low-Write-Amplification Cache for Tiny Objects on Log-Structured Flash Devices · ASPLOS (2) 2026
Storage systems › flash and SSD
write amplification reduction
1.012026
Nemo: A Low-Write-Amplification Cache for Tiny Objects on Log-Structured Flash Devices · ASPLOS (2) 2026
Storage systems
storage reliability
0.312026
Nemo: A Low-Write-Amplification Cache for Tiny Objects on Log-Structured Flash Devices · ASPLOS (2) 2026

Methods — techniques the papers use, named apart from their topics

tiny object caching · 1.0
YearPublicationVenuePosition
2026 Nemo: A Low-Write-Amplification Cache for Tiny Objects on Log-Structured Flash Devices
Xufeng Yang, Jingxin Hu, Congming Gao, Tianyang Jiang, Linbo Long, Yina Lv, Jiwu Shu
ASPLOS (2)1
2026 LOONG: Utilizing Long-Stride Reprogramming to Enhance the Performance of SSDs
Congming Gao, Jiancong Zheng, Xufeng Yang, Qiao Li 0001, Yina Lv, Chun Jason Xue, Jiwu Shu
ISCA3
2024 In-place Switch: Reprogramming based SLC Cache Design for Hybrid 3D SSDs
abstract
To increase SSD capacity, high bit-density cells, such as Triple-Level Cell (TLC), are utilized within 3D SSDs. However, due to the inferior performance of TLC, SLC/TLC hybrid 3D SSD is designed to use a portion of the TLC space as an SLC cache to achieve high SSD performance by writing host data at the SLC speed. However, our preliminary studies indicate that the SLC cache can lead to a performance cliff if filled rapidly and cause significant write amplification when data migration occurs during idle times. In this work, we propose leveraging a reprogram operation to address these challenges. Specifically, when the SLC cache is full or during idle periods, a reprogram operation is performed to switch used SLC pages to TLC pages in place (termed In-place Switch, IPS). Subsequently, other free TLC space is allocated as the new SLC cache. IPS can continuously provide sufficient SLC cache within SSDs, significantly improving write performance and reducing write amplification. Experimental results demonstrate that IPS can reduce write latency and write amplification by up to 0.75 times and 0.53 times, respectively, compared to state-of-the-art SLC cache technologies.
Xufeng Yang, Jiancong Zheng, Cheng Ji 0002, Congming Gao
NAS1