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Sadullah Canakci

dblp:216/7277 · DBLP profile ↗
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6ranked-venue papers
3as first author
4since 2021 · last 2022
0000-0002-2855-7818ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 4 · 2 first-author · 2 since 2021Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 93% Processor architecture and microarchitecture · 7%
Network and information security
1 paper
Hardware security and side channels · 100%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › test generation
directed test generation
0.512021
DirectFuzz: Automated Test Generation for RTL Designs using Directed Graybox Fuzzing · DAC 2021
Electronic design automation
hardware verification and test
0.512021
DirectFuzz: Automated Test Generation for RTL Designs using Directed Graybox Fuzzing · DAC 2021
Electronic design automation › hardware verification and test › functional verification
RTL verification
0.512021
DirectFuzz: Automated Test Generation for RTL Designs using Directed Graybox Fuzzing · DAC 2021
Hardware security and side channels
hardware monitoring
0.412020
PHMon: A Programmable Hardware Monitor and Its Security Use Cases · USENIX Security Symposium 2020
Electronic design automation › hardware verification and test
coverage-driven verification
0.112021
DirectFuzz: Automated Test Generation for RTL Designs using Directed Graybox Fuzzing · DAC 2021

Methods — techniques the papers use, named apart from their topics

directed graybox fuzzing · 0.5
YearPublicationVenuePosition
2022 TargetFuzz: Using DARTs to Guide Directed Greybox Fuzzers
abstract
Software development is a continuous and incremental process. Developers continuously improve their software in small batches rather than in one large batch. The high frequency of small batches makes it essential to use effective testing methods that detect bugs under limited testing time. To this end, researchers propose directed greybox fuzzing (DGF) which aims to generate test cases towards stressing certain target sites. Different from the coverage-based greybox fuzzing (CGF) which aims to maximize code coverage in the whole program, the goal of DGF is to cover potentially buggy code regions (e.g., a recently modified program region). While prior works improve several aspects of DGF (such as power scheduling, input prioritization, and target selection), little attention has been given to improving the seed selection process. Existing DGF tools use seed corpora mainly tailored for CGF (i.e., a set of seeds that cover different regions of the program). We observe that using CGF-based corpora limits the bug-finding capability of a directed greybox fuzzer. To mitigate this shortcoming, we propose TargetFuzz, a mechanism that provides a DGF tool with a target-oriented seed corpus. We refer to this corpus as DART corpus, which contains only 'close' seeds to the targets. This way, DART corpus guides DGF to the targets, thereby exposing bugs even under limited fuzzing time. Evaluations on 34 real bugs show that AFLGo (a state-of-the-art directed greybox fuzzer), when equipped with DART corpus, finds 10 additional bugs and achieves $4.03x speedup, on average, in the time-to-exposure compared to a generic CGF-based corpus.
Sadullah Canakci, Nikolay Matyunin, Kalman Graffi, Ajay Joshi, Manuel Egele
AsiaCCS1
2021 FlexFilt: Towards Flexible Instruction Filtering for Security
abstract
As the complexity of software applications increases, there has been a growing demand for intra-process memory isolation. The commercially available intra-process memory isolation mechanisms in modern processors, e.g., Intel’s memory protection keys, trade-off between efficiency and security guarantees. Recently, researchers have tended to leverage the features with low security guarantees for intra-process memory isolation. Subsequently, they have relied on binary scanning and runtime binary rewriting to prevent the execution of unsafe instructions, which improves the security guarantees. Such intra-process memory isolation mechanisms are not the only security solutions that have to prevent the execution of unsafe instructions in untrusted parts of the code. In fact, we identify a similar requirement in a variety of other security solutions. Although binary scanning and runtime binary rewriting approaches can be leveraged to address this requirement, it is challenging to efficiently implement these approaches.
Leila Delshadtehrani, Sadullah Canakci, William Blair, Manuel Egele, Ajay Joshi
ACSAC2
2021 DirectFuzz: Automated Test Generation for RTL Designs using Directed Graybox Fuzzing
abstract
A critical challenge in RTL verification is to generate effective test inputs. Recently, RFUZZ proposed to use an automated software testing technique, namely Graybox Fuzzing, to effectively generate test inputs to maximize the coverage of the whole hardware design. For a scenario where a tiny fraction of a large hardware design needs to be tested, the RFUZZ approach is extremely time consuming. In this work, we present DirectFuzz, a directed test generation mechanism. DirectFuzz uses Directed Graybox Fuzzing to generate test inputs targeted towards a module instance, which enables targeted testing. Our experimental results show that DirectFuzz covers the target sites up to 17.5 × faster (2.23 × on average) than RFUZZ on a variety of RTL designs.
Sadullah Canakci, Leila Delshadtehrani, Furkan Eris, Michael B. Taylor, Manuel Egele, Ajay Joshi
DAC1
2021 SealPK: Sealable Protection Keys for RISC-V
abstract
With the continuous increase in the number of software-based attacks, there has been a growing effort towards isolating sensitive data and trusted software components from untrusted third-party components. Recently, Intel introduced a new hardware feature for intra-process memory isolation, called Memory Protection Keys (MPK). The limited number of unique domains (16) provided by Intel MPK prohibits its use in cases where a large number of domains are required. Moreover, Intel MPK suffers from the protection key use-after-free vulnerability. To address these shortcomings, in this paper, we propose an efficient intra-process isolation technique for the RISC-V open ISA, called SeaIPK, which supports up to 1024 unique domains. Additionally, we devise three novel sealing features to protect the allocated domains, their associated pages, and their permissions from modifications or tampering by an attacker. We demonstrate the efficiency of SealPK by leveraging it to implement an isolated secure shadow stack on an FPGA prototype.
Leila Delshadtehrani, Sadullah Canakci, Manuel Egele, Ajay Joshi
DATE2
2020 Efficient Context-Sensitive CFI Enforcement Through a Hardware Monitor
Sadullah Canakci, Leila Delshadtehrani, Boyou Zhou, Ajay Joshi, Manuel Egele
DIMVA1
2020 PHMon: A Programmable Hardware Monitor and Its Security Use Cases
Leila Delshadtehrani, Sadullah Canakci, Boyou Zhou, Schuyler Eldridge, Ajay Joshi, Manuel Egele
USENIX Security Symposium2