Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Nayeon Kim 0006

dblp:218/1515-6 · DBLP profile ↗
← Back
3ranked-venue papers
2as first author
3since 2021 · last 2024
0000-0002-3567-5708ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021Systems, architecture and hardware · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 64% Hardware accelerators and domain-specific architectures · 28% Cloud and datacenter computing · 8%
Artificial intelligence
1 paper
Autonomous driving · 61% Video understanding and tracking · 39%

Topics — the 6 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Robotics › Autonomous driving
HD map construction
0.812024
Unveiling the Hidden: Online Vectorized HD Map Construction with Clip-Level Token Interaction and Propagation · NeurIPS 2024
Computer vision › Video understanding and tracking › temporal modeling
temporal fusion
0.812024
Unveiling the Hidden: Online Vectorized HD Map Construction with Clip-Level Token Interaction and Propagation · NeurIPS 2024
Robotics › Autonomous driving › HD map construction
vectorized map construction
0.812024
Unveiling the Hidden: Online Vectorized HD Map Construction with Clip-Level Token Interaction and Propagation · NeurIPS 2024
Hardware accelerators and domain-specific architectures › machine learning accelerator › transformer accelerator
LLM inference accelerator
0.812024
An LPDDR-based CXL-PNM Platform for TCO-efficient Inference of Transformer-based Large Language Models · HPCA 2024
Memory systems › processing-in-memory
near-memory processing
0.812024
An LPDDR-based CXL-PNM Platform for TCO-efficient Inference of Transformer-based Large Language Models · HPCA 2024
Memory systems
processing-in-memory
0.812024
An LPDDR-based CXL-PNM Platform for TCO-efficient Inference of Transformer-based Large Language Models · HPCA 2024

Methods — techniques the papers use, named apart from their topics

token propagation · 0.8token interaction · 0.8software stack · 0.8LPDDR5X · 0.8CXL interconnect · 0.8
YearPublicationVenuePosition
2024 An LPDDR-based CXL-PNM Platform for TCO-efficient Inference of Transformer-based Large Language Models
abstract
Transformer-based large language models (LLMs) such as Generative Pre-trained Transformer (GPT) have become popular due to their remarkable performance across diverse applications, including text generation and translation. For LLM training and inference, the GPU has been the predominant accelerator with its pervasive software development ecosystem and powerful computing capability. However, as the size of LLMs keeps increasing for higher performance and/or more complex applications, a single GPU cannot efficiently accelerate LLM training and inference due to its limited memory capacity, which demands frequent transfers of the model parameters needed by the GPU to compute the current layer(s) from the host CPU memory/storage. A GPU appliance may provide enough aggregated memory capacity with multiple GPUs, but it suffers from frequent transfers of intermediate values among GPU devices, each accelerating specific layers of a given LLM. As the frequent transfers of these model parameters and intermediate values are performed over relatively slow device-to-device interconnects such as PCIe or NVLink, they become the key bottleneck for efficient acceleration of LLMs. Focusing on accelerating LLM inference, which is essential for many commercial services, we develop CXL-PNM, a processing near memory (PNM) platform based on the emerging interconnect technology, Compute eXpress Link (CXL). Specifically, we first devise an LPDDR5X-based CXL memory architecture with 512GB of capacity and 1.1TB/s of bandwidth, which boasts 16× larger capacity and 10× higher bandwidth than GDDR6and DDR5-based CXL memory architectures, respectively, under a module form-factor constraint. Second, we design a CXLPNM controller architecture integrated with an LLM inference accelerator, exploiting the unique capabilities of such CXL memory to overcome the disadvantages of competing technologies such as HBM-PIM and AxDIMM. Lastly, we implement a CXLPNM software stack that supports seamless and transparent use of CXL-PNM for Python-based LLM programs. Our evaluation shows that a CXL-PNM appliance with 8 CXL-PNM devices offers 23% lower latency, 31% higher throughput, and 2.8× higher energy efficiency at 30% lower hardware cost than a GPU appliance with 8 GPU devices for an LLM inference service.
Sangsoo Park, Kyungsoo Kim 0003, Jinin So, Jin Jung, Jonggeon Lee, Kyoungwan Woo, Nayeon Kim 0006, Younghyun Lee, Hyungyo Kim, Yongsuk Kwon, Jinhyun Kim, Yeongon Cho, Yongmin Tai, Jeonghyeon Cho, Hoyoung Song, Jung Ho Ahn, Nam Sung Kim
HPCA7
2024 Unveiling the Hidden: Online Vectorized HD Map Construction with Clip-Level Token Interaction and Propagation
abstract
Predicting and constructing road geometric information (e.g., lane lines, road markers) is a crucial task for safe autonomous driving, while such static map elements can be repeatedly occluded by various dynamic objects on the road. Recent studies have shown significantly improved vectorized high-definition (HD) map construction performance, but there has been insufficient investigation of temporal information across adjacent input frames (i.e., clips), which may lead to inconsistent and suboptimal prediction results. To tackle this, we introduce a novel paradigm of clip-level vectorized HD map construction, MapUnveiler, which explicitly unveils the occluded map elements within a clip input by relating dense image representations with efficient clip tokens. Additionally, MapUnveiler associates inter-clip information through clip token propagation, effectively utilizing long- term temporal map information. MapUnveiler runs efficiently with the proposed clip-level pipeline by avoiding redundant computation with temporal stride while building a global map relationship. Our extensive experiments demonstrate that MapUnveiler achieves state-of-the-art performance on both the nuScenes and Argoverse2 benchmark datasets. We also showcase that MapUnveiler significantly outperforms state-of-the-art approaches in a challenging setting, achieving +10.7% mAP improvement in heavily occluded driving road scenes. The project page can be found at https://mapunveiler.github.io.
Nayeon Kim 0006, Hongje Seong, Daehyun Ji, Sujin Jang
NeurIPS1
2023 D-3DLD: Depth-Aware Voxel Space Mapping for Monocular 3D Lane Detection with Uncertainty
abstract
The estimation of 3D lanes from monocular RGB images is a fundamentally ill-posed problem. Previous studies have assumed that all lanes are on a flat ground plane. However, we argue that the algorithms based on this assumption have difficulty in detecting various lanes in actual driving environments. Contrary to previous approaches, we expand rich contextual features from an image domain to a 3D space by utilizing depth-aware voxel mapping. In addition, we determine 3D lanes based on voxelized features. We design a new lane representation combined with uncertainties and predict the confidence intervals of 3D lane points using Laplace loss. Experimental results show that the proposed method achieves state-of-the-art detection accuracy on three challenging datasets, including two real-world datasets, and significantly outperforms existing methods with reasonable computation load.
Nayeon Kim 0006, Moonsub Byeon, Daehyun Ji, Dokwan Oh
ICASSP1