This paper presents Si/SiGe:C and InP/GaAsSb HBTs which feature specific assets to address submillimeter-wave and THz applications. Process and modeling status and challenges are reviewed. The specific topics of thermal and substrate effects, reliability, and HF measurements are also discussed.

This letter presents the characterisation of a GFET transistor with a source-pull/load-pull test bench. The characterisation shows that despite the good fTand fMAX, it is hard to achieve reasonable power gain using the GFET device in a circuit configuration. This is due to the very high impedance at the gate making impedance matching at the input extremely difficult. An electrical model is used to evaluate the optimum power gain of the transistor under matched conditions. In a second part, a benchmarking of the technology is realized through accurate simulation of an optimised GFET device. Based on this input data, a compact model permits the evaluation of the GFET for high frequency amplifications.

With the increase in the design complexity of MPSoC architectures, estimating power consumption is very complex and time consuming at lower level of abstraction. We propose a methodology using ArchC named Power-ArchC for a fast high-level estimation of processor power consumption. Power values are obtained by an instruction level power characterization at gate level. The requirements for power evaluation infrastructure are compatible processor models written in ArchC and RTL, and the Technology library. We show power results for a 32-bit MIPS processor with different benchmarks, based on 45nm technology.