With the maturity of CMOS technologies and their use in low-voltage analog applications, the accuracy of SPICE models is very important. Here, an extremely accurate yet simple form of the charge-sheet model is developed using a symmetric polynomial interpolation of the charge in the channel. This formulation of the drain current retains the same simplicity of the industry-standard surface potential MOSFET models based on the symmetric linearization method (SLM). But, unlike the SLM, it is developed without requiring the linearization of the charge in the channel, hence, the asymmetries and the nonlinearity are accurately accounted for. The model, although more accurate, has the same computational efficiency and easy implementation of the SLM. Finally, the equations of the currents and terminal charges can be worked out to have the same mathematical form as the SLM.

This paper presents a 0.2V VCO-based OTA (VCO-OTA) for low-voltage, low-power applications. The VCO-OTA processes information in the time domain, which makes it possible to scale down supply to really low voltages. The proposed architecture eliminates current sources used in the charge pump to design a 0.2V VCO-OTA. Simulations show that in unity gain configuration, the proposed architecture achieves 60kHz unity gain bandwidth and 207μVRMs input referred noise while consuming 492nW.

In practical printed circuit board (PCB) designs, electromagnetic interference (EMI) is coupled from the ground plane, which is commonly shared among the analog, digital, and mixed-signal integrated circuits. This noisy ground plane couples interference capacitively to all the IC pins, including the output: this effect is exacerbated when the IC is connected to long wires and traces that are routed close to the conductive ground plane. This paper reports on the effect of interference, which is coupled capacitively from the PCB ground plane into all the IC pins of an opamp connected as a voltage buffer. Simulations illustrate the susceptibilities in custom operational amplifier designs, and are corroborated by measurements on several commercial devices. These measurements show that the EMI-induced offset can attain considerable values for the most critical EMI frequencies, which lie between 10 and 100 MHz. Moreover, these illustrate that there is a considerable susceptibility of operational amplifiers to electromagnetic interference coupled to their output pins.

In this paper, we present two charge pump architectures for nonvolatile memories with dynamic biasing of the gate and the body voltages. By controlling the gate and the body voltage of each pass-transistor, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the following with a negligible voltage drop and large conductivity. The charge pumps were fabricated in the ST 130-nm digital standard CMOS technology. Compared to conventional charge pumps, larger output voltage and better power efficiency are achieved still retaining a simple two-phase clocking scheme. Measurements performed on four-stage and eight-stage charge pumps are provided.

A new charge pump circuit is presented: it is based on PMOS pass transistors with dynamic control of the gate and body voltages. By controlling the gate and the bulk of each pass-transistor, the voltage loss due to the device threshold is removed and the charge is pumped from one stage to the other with negligible voltage drop. Compared to conventional charge pumps, it exhibits a larger output voltage and better power efficiency still retaining a simple two-phase clocking scheme. The architecture is based on low-voltage transistors and the voltage drop among the device terminals does not exceed the supply voltage. Measurements performed on a 4-stage charge pump, fabricated exploiting a ST 130nm CMOS process, are provided.

This paper presents the successful design of a CMOS operational amplifier with enhanced immunity to electromagnetic interferences. Thanks to its strongly symmetrical topology, the amplifier exhibits an intrinsic robustness to interferences arising from a wide class of sources. Such a scheme, for the first time in the authors' knowledge, proves the effectiveness of symmetrical topologies to minimize the effects of electromagnetic interferences in operational amplifiers. The amplifier architecture is based on 2 identical stages: 2 fully differential source cross-coupled amplifiers with active loads. The circuit was fabricated in a 0.8 /spl mu/m n-well CMOS technology (AMS CYE process). Experimental results, in terms of EMI immunity, are presented and compared with a commercial amplifier. They show a low susceptibility to EMI conveyed both to the input and the power pins. The EMI effects on the proposed amplifier are reduced by more than one order of magnitude, compared to a commercial amplifier. Furthermore the amplifier overall measured performances are provided along with the corresponding simulation results.